DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Objections
Claim 17 is objected to because of the following informalities. Appropriate correction is required.
Claim 17 does not set forth a “first plurality of values” and “second plurality of value” before a “third plurality of values” on line 7.
Claim Rejections - 35 USC § 112
Claims 3-6, 11-16, 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 recites limitations “wherein the positive polarity subthreshold voltage is applied to the memory cells of the second group that are programmed to the first data state” on lines 1-3. There appears the specification does not support these limitations. From FIG. 3, the positive polarity subthreshold voltage of +3.6V is applied to the memory cells of the second group that are programmed to the first data state, such as memory cells 333-1, 333-2. However, the positive polarity subthreshold voltage of +3.6V is also applied the memory cells of the second group that are programmed to the second data state, such as memory cells 332-1, 332-2 and 332-3.
Claim 4 recites limitations “wherein the circuitry is configured to apply a ground voltage to the memory cells of the second group that are programmed to the second data state while the positive polarity subthreshold voltage is applied to the memory cells of the second group that are programmed to the first data state” on lines 1-5. Specification also does not support these limitations. From FIG. 3, the ground voltage GND is applied to the memory cells of the second group that are programmed to the first data state, such as memory cells 325-2, 325-8. However, the ground voltage GND is also applied the memory cells of the second group that are programmed to the second data state, such as memory cells 325-3.
Claims 5-6 and 10 are rejected for the same reasons set forth above as they recite similar limitations.
Claim 11 recites limitations “applying a positive polarity voltage to memory cells of a second group of memory cells of the memory array that are programmed to the first data state; applying a negative polarity voltage to memory cells of the second group that are programmed to the second data state, wherein the second group of memory cells is programmed to a weight vector comprising a second plurality of values corresponding to a second plurality of data states” on lines 6-11. Claim 11 is rejected for the same reasons set forth above as it recites similar limitations.
Claim 18 recites:
“an additional weight vector with a third plurality of values” on line 2. It is not clear if that is any different from “an additional weight vector with a third plurality of values” in claim 17, line 7.
“the another weight vector” on line 4. There is insufficient antecedent basis for this limitation in the claim. It is also not clear to Examiner if “the another weight vector” is any different from “an additional weight vector” on line 2.
Examiner is temporarily not considering claims 3-6, 11-16, 18-20 under a prior art rejection due to the 112 rejection, first paragraph, outlined above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-9, 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,395,738 to Castro (hereafter Castro) in view of PGPub. 2015/0088797 to Kim et al. (hereafter Kim).
Regarding independent claim 1, Castro teaches an apparatus, comprising:
a memory array including a plurality of memory cells (FIG. 4: memory array 400), wherein each of the plurality of memory cells is programmable to a first data state or a second data state (i.e. high resistance state and low resistance state); and
circuitry coupled to the memory array (FIG. 12: all elements except memory array 1206), wherein the circuity is configured to:
provide an input vector FIG. 4: input vector 402);
apply a subthreshold voltage to each of a second group of memory cells of the memory array (FIG. 4: positive polarity voltage differential VDM1 or negative polarity voltage differential VDM2), wherein the second group of memory cells is programmed to a weight vector comprising a second number of data states (FIG. 4: see data state in each of the memory cells of memory array 400) and wherein the subthreshold voltage is based upon the data states of the input vector (FIGS. 2A and 4: VDM1 is considered subthreshold voltage with respect to input vector components Bit0, Bit1, Bit4, Bit5, and VMD2 is considered subthreshold voltage with respect to input vector components Bit2, Bit3, Bit6, Bit7); and
map the input vector to a location in the memory array using the weight vector after applying the subthreshold voltage (FIG. 4: by detecting match/mismatch signals responsive to latches 440-0 to 440-7).
Castro does not teach the strikethrough limitations.
Kim teaches synapse circuits comprising pre-synaptic neuron circuit inherently comprising a first group of memory cells, a synapse circuit comprising a second group of memory cells, and a post-synaptic neuron circuit inherently comprising a third group of memory cells (FIGS. 2 and 4A: 100, 200, and 300 respectively). The synapse circuits are controlled by encoding an input vector comprising a first number of data states to be programmed to a first group of memory cells of the memory array (FIG. 1: output vector from pre-synaptic neuron circuits 100, which is used as input to synapse circuits 10).
Since Castro and Kim are both from the same field of endeavor, the purpose disclosed by Kim would have been recognized in the pertinent art of Castro.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that the memory device of Castro can be used for neural network. It is obvious that in neural network, the input vector of a current layer corresponding to weight vector stored in previous layer.
Regarding dependent claim 2, Castro teaches wherein the circuity is configured to apply the subthreshold voltage in a positive polarity and a negative polarity (FIG. 4: positive polarity voltage differential VDM1 or negative polarity voltage differential VDM2).
Regarding dependent claim 7, Castro implicitly teaches wherein the circuity is configured to determine a total current flow resultant from applying the positive polarity subthreshold voltage and a total current flow resultant from applying the negative polarity subthreshold voltage (FIG. 4: because the currents generated from each of the memory cells are sent to the corresponding sense amplifier at the same time).
Regarding dependent claim 8, Castro teaches wherein the circuity is configured to: compare the total current flow resultant from applying the positive polarity subthreshold voltage to the total current flow resultant from applying the negative polarity subthreshold voltage (sensing total current on each of the word lines by detecting snapback event, see 9:55-10:43); and map the input vector to the location in the memory based on a result of the comparison (FIG. 4: by detecting match/mismatch signals responsive to latches 440-0 to 440-7).
Regarding dependent claim 9, Castro teaches wherein each of the plurality of memory cells is programmable to a third data state (FIG. 2A: state D).
Regarding independent claim 17, Castro teaches an apparatus, comprising:
a memory array including a plurality of memory cells, wherein each of the plurality of memory cells is programmable to a first data state, a second data state, or a third data state (FIG. 2A: states 0, 1 and D); and
circuitry coupled to the array of memory cells (FIG. 12: all elements except memory array 1206), wherein the circuitry is configured to:
providing an FIG. 4: input vector 402);
apply a positive polarity subthreshold voltage to memory cells of the array corresponding to vector component positions of the FIGS. 2A and 4: positive polarity voltage differential VDM1 is considered subthreshold voltage with respect to input vector components Bit0, Bit1, Bit4, Bit5);
apply a negative polarity subthreshold voltage to memory cells of the array corresponding to vector component positions of the FIGS. 2A and 4: negative polarity voltage differential VMD2 is considered subthreshold voltage with respect to input vector components Bit2, Bit3, Bit6, Bit7);
apply a TAB LE 1: when the input state is Z, applied voltage is regardless, see 6:64-66); and
map the input vector to an additional location in the memory array (FIG. 4: memory array 400) using the additional weight vector after applying the positive polarity subthreshold voltage, the negative polarity subthreshold voltage, and the ground subthreshold voltage (FIG. 4: by detecting match/mismatch signals responsive to latches 440-0 to 440-7).
Castro does not teach the strikethrough limitations.
Kim teaches synapse circuits comprising pre-synaptic neuron circuit inherently comprising a first group of memory cells, a synapse circuit comprising a second group of memory cells, and a post-synaptic neuron circuit inherently comprising a third group of memory cells (FIGS. 2 and 4A: 100, 200, and 300 respectively). The synapse circuits are controlled by encoding an input vector comprising a first number of data states to be programmed to a first group of memory cells of the memory array (FIG. 1: output vector from pre-synaptic neuron circuits 100, which is used as input to synapse circuits 10).
Since Castro and Kim are both from the same field of endeavor, the purpose disclosed by Kim would have been recognized in the pertinent art of Castro.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that the memory device of Castro can be used for neural network. It is obvious that in neural network, the input vector of a current layer corresponding to weight vector stored in previous layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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July 1, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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