DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Product-by-Process Limitations
While not objectionable, the Office reminds applicant that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, in re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. Note that applicant has the burden of proof in such cases, as the above case law makes clear. Thus, no patentable weight will be given to those process steps which do not add structural limitations to the final product.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-10, 12-15, 19-24, 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Zhai et al. (US PUB. 2016/0260684) in view of Xu et al. (US Patent 8,575,493) and FONG et al. (US PUB. 2017/0301657).
Regarding claim 1, Zhai teaches a three-dimensional integrated circuit device, comprising:
an interconnect network layer (see the Examiner’s annotations in Fig. 12 below) having a first plurality of electrodes on a lower surface, a second plurality of electrodes on an upper surface, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes (see Fig. 12 below);
a lower device structure (see the Examiner’s annotations in Fig. 12 below) with upper electrodes respectively bonded to electrodes of the first plurality of electrodes on the lower surface of the interconnect network layer (Fig. 12 below); and
an upper device structure (see the Examiner’s annotations in Fig. 12 below) with lower electrodes (see unlabeled electrodes under 110, 116 & 110) respectively bonded to electrodes of the second plurality of electrodes on the upper surface of the interconnect network layer (see Fig. 12 and note the Examiner’s annotation), and
wherein the lower device structure comprises a first semiconductor device (e.g. 150), and the upper device structure comprises a second semiconductor device (e.g. 110, 116 and/or 110).
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Zhai is silent on (i) wherein a thickness of the interconnect network layer is less than 3 pm; and (ii) wherein the semiconductor device is a three-dimensional integrated circuit device.
Xu teaches a semiconductor device, wherein a thickness of an interconnect network layer is less than 3 µm (column 4, lines 19-25). This improves further miniaturization that saves precious real estate. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the interconnect network layer (RDL) dimensions, as taught by Xu, so as to further miniaturize to save space on a semiconductor chip. Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
FONG teaches (ii) a semiconductor device that is a three-dimensional integrated circuit device (e.g. Para [0103, 0105 & 0107]). 3DIC stacking has known advantages that allows further miniaturization that saves precious real estate and enhances performance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the 3DIC stacking, as taught by FONG, so as save space and enhance performance.
Regarding claim 2 the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein the interconnect network layer is formed by: forming the second plurality of electrodes, the plurality of connection structures, and the first plurality of electrodes on a substrate; implanting ions into the substrate to form a cleave plane in the substrate; and cleaving the substrate at the cleave plane (See Fig. 16 and the associated Fig. 3-5 and respective texts). Further, the above limitation (bolded) is a product by process limitation and does not result to a structurally distinguishable product over the prior art.
Regarding claim 3, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 2, wherein the interconnect network layer (see interconnect network layer in Fig. 9i) is bonded to the lower device structure before cleaving the substrate (regardless of before or after the process of cleaving, in the final structure, the interconnect structure is bonded to the lower device structure).
Regarding claim 5, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein the connection structures include a through silicon via with a diameter of 20-200 nm (FONG’s Para [0225]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 6, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 5, wherein the connection structures include a through silicon via with an aspect ratio (depth : width) of 2:1 or greater (e.g. FONG’s Para [0219]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 7, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 6, wherein the through silicon via has a depth of 1 µm or less (FONG’s Para [0225]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 8, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein a thickness of the interconnect network layer is from 0.2 to 2 um (Xu’s column 4, lines 19-25). Also, FONG teaches a 3DIC stacking (e.g. Para [0103, 0105 & 0107]), wherein a thickness of an interconnect network layer is less than 3 µm (FONG’s Para [0153-0154]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 9, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein a thickness of the interconnect network layer is from 0.2 to 2 µm (Xu’s column 4, lines 19-25), and the connection structures include at least one through silicon via with a diameter of 20-200 nm (Fong’s Para [0225]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 10, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein the first plurality of electrodes of the interconnect network has an IO density (pins/cm^2) of 1,000,000 to 100,000,000 and a pin pitch of 10,000 -1,000 nm (FONG’s Para [0225]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 12, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, further comprising at least one cooling channel (FONG’s Para [0010, 0042 & 0094-0095] & Fig. 16 to cool the device to mitigate overheating).
Regarding claim 13 the combination of Zhai, Xu and FONG teaches the 3DIC of claim 12, wherein the cooling channel is coated with a material having a higher thermal conductivity than the material underlaying the coating (e.g. second photoresist layer on a cooling channel as discussed in FONG’s Para [0094] & Fig. 16).
Regarding claim 14, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 12, wherein the cooling channel is coated with an oxide material or a nitride material (photoresist material can be either nitride or oxide).
Regarding claim 15, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 14, wherein the cooling channel is coated with silicon oxide or silicon nitride (FONG’s Fig. 16, photoresist can be silicon nitride or silicon oxide).
Regarding claim 19, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 12, further comprising a fluid in the cooling channel, wherein the fluid is a heat transfer fluid (note the cooling channel in FONG’s Fig. 16, wherein the fluid is understood to be a heat transfer fluid).
Regarding claim 20, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein the interconnect network layer comprises a plurality of lateral connections (note the lateral connections in FONG’s Fig. 6-9).
Regarding claim 21, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 20, wherein a lateral connection of the plurality of lateral connections couples a first via of the upper device structure to a second via of the upper device structure (FONG’s Fig. 7-8).
Regarding claim 22, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein at least one of the lower device structure and the upper device structure comprises two die-scale semiconductor devices, and the two die-scale semiconductor devices have different sizes (Fig. 12).
Regarding claim 23, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein at least one of the upper device structure and the lower device structure includes one or more of an optical sensor, a radio frequency tuner, an amplifier, and a light emitting diode (e.g. Zhai’s para [0038]).
Regarding claim 24, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 23, wherein at least one of the upper device structure and the lower device structure is a memory device (e.g. Zhai’s para [0038]).
Regarding claim 29, the combination of Zhai, Xu and FONG teaches the 3DIC of claim 1, wherein the interconnect network layer is cleaved from a silicon substrate (FONG teaches wherein an interconnect network layer is cleaved from a silicon substrate (FONG’s Fig. 3-6).
Regarding claim 30, Zhai teaches a three-dimensional integrated circuit device, comprising:
an interconnect network layer (see the Examiner’s annotations in Fig. 12 above) having a first plurality of electrodes on a lower surface, a second plurality of electrodes on an upper surface, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes (see Fig. 12 above);
a lower device structure (see the Examiner’s annotations in Fig. 12 below) with upper electrodes respectively bonded to electrodes of the first plurality of electrodes on the lower surface of the interconnect network layer (Fig. 12 above); and
an upper device structure (see the Examiner’s annotations in Fig. 12 below) with lower electrodes (see unlabeled electrodes under 110, 116 & 110) respectively bonded to electrodes of the second plurality of electrodes on the upper surface of the interconnect network layer (see Fig. 12 and note the Examiner’s annotation), and
wherein the lower device structure comprises a first semiconductor device (e.g. 150), and the upper device structure comprises a second semiconductor device (e.g. 110, 116 and/or 110).
Zhai is silent on (i) wherein a thickness of the interconnect network layer is less than 3 pm; and (ii) wherein the semiconductor device is a three-dimensional integrated circuit device and wherein the integrated circuit device comprising at least one cooling channel..
Xu teaches (i) a semiconductor device, wherein a thickness of an interconnect network layer is less than 3 µm (column 4, lines 19-25). This improves further miniaturization that saves precious real estate. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the interconnect network layer (RDL) dimensions, as taught by Xu, so as to further miniaturize to save space on a semiconductor chip. Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
FONG teaches (ii) an integrated device in a 3DIC stacking (e.g. Para [0103, 0105 & 0107]) comprising at least one cooling channel (Para [0010]). The cooling channel cools the device to mitigate overheating. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the 3DIC stacking and use of cooling channel, as taught by FONG, so as save space, mitigate overheating and enhance performance.
Regarding claim 31, Zhai teaches a three-dimensional integrated circuit device, comprising:
an interconnect network layer (see the Examiner’s annotations in Fig. 12 above) having a first plurality of electrodes on a lower surface, a second plurality of electrodes on an upper surface, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes (see Fig. 12 above);
a lower device structure (see the Examiner’s annotations in Fig. 12 below) with upper electrodes respectively bonded to electrodes of the first plurality of electrodes on the lower surface of the interconnect network layer (Fig. 12 above); and
an upper device structure (see the Examiner’s annotations in Fig. 12 below) with lower electrodes (see unlabeled electrodes under 110, 116 & 110) respectively bonded to electrodes of the second plurality of electrodes on the upper surface of the interconnect network layer (see Fig. 12 and note the Examiner’s annotation),
wherein the upper device structure includes at least two die-scale device (110, 116 and/or 110), and
wherein the lower device structure comprises a first semiconductor device (e.g. 150), and the upper device structure comprises a second semiconductor device (e.g. 110, 116 and/or 110).
Zhai is silent on (i) wherein a thickness of the interconnect network layer is less than 3 pm; and (ii) wherein the semiconductor device is a three-dimensional integrated circuit device.
Xu teaches a semiconductor device, wherein a thickness of an interconnect network layer is less than 3 µm (column 4, lines 19-25). This improves further miniaturization that saves precious real estate. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the interconnect network layer (RDL) dimensions, as taught by Xu, so as to further miniaturize to save space on a semiconductor chip. Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
FONG teaches (ii) a semiconductor device that is a three-dimensional integrated circuit device (e.g. Para [0103, 0105 & 0107]). 3DIC stacking has known advantages that allows further miniaturization that saves precious real estate and enhances performance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai with the 3DIC stacking, as taught by FONG, so as save space and enhance performance.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhai, Xu and FONG as applied to claim 1 above, and in further view of Wu et al. (US PUB. 2020/0058617).
Regarding claim 11, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 1, wherein the interconnect network layer is hybrid bonded to the lower device structure and the upper device structure. However, Wu teaches in Fig. 4, wherein an interconnect network layer 132 is hybrid bonded to a lower device structure 10 and an upper device structure 20. This has the advantage of shortening process steps and manufacturing period. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai/Xu/FONG with the hybrid bonding, as taught by Wu, so as to reduce manufacturing duration.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhai, Xu and FONG as applied to claim 12 above, and in further view of Wagner et al. (US PUB. 2013/0235527).
Regarding claim 16, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 12, wherein the cooling channel includes a carbon-based material. However Wagner teaches in Fig. 1-3 and Para [0033], wherein a cooling channel 220 includes a carbon-based material. This has the advantage of obtaining a device with improved thermal conductivity. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai/Xu/FONG with the carbon-based material for the cooling channel, as taught by Wagner, so as to obtain a device with enhanced thermal characteristics.
Regarding claim 17, the combination of Zhai, Xu, FONG and Wagner teaches the 3DIC of claim 16, wherein the carbon-based material includes at least one of a diamond material, an amorphous carbon material, a graphite material and (Wagner’s Para [0032-0033]).
Regarding claim 18, perhaps in the interest of brevity, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 12, further comprising a fluid in the cooling channel, wherein the fluid includes water. However Wagner teaches the widely known use of water as coolant in Para [0027 & 0034]. Wagner teaches a fluid in the cooling channel, wherein the fluid includes water. This has the advantage of obtaining a device with improved thermal conductivity. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai/Xu/FONG with the use of water, as taught by Wagner, so as to obtain a device with enhanced thermal characteristics.
Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Zhai, Xu and FONG as applied to claim 1 above, and in further view of Liao et al. (US Patent 11,515,278).
Regarding claim 27, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 1, wherein at least one of the plurality of connection structures couples an electrode of the first plurality of electrodes to another electrode of the first plurality of electrodes. However Liao teaches wherein at least one of the connection structures couples an electrode of the first plurality of electrodes to another electrode of the first plurality of electrodes (see Fig. 1). This has the advantage of providing an alternative design for conductive pathways. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai/Xu/FONG with the conductive connection/traces, as taught by Liao, so as to obtain a device with an alternative conductive pathways.
Regarding claim 28, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 1, wherein at least one of the plurality of connection structures couples an electrode of the second plurality of electrodes to another electrode of the second plurality of electrodes. However Liao teaches wherein at least one of the connection structures couples an electrode of the second plurality of electrodes to another electrode of the second plurality of electrodes (see Fig. 1). This has the advantage of providing an alternative design for conductive pathways. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Zhai/Xu/FONG with the conductive connection/traces, as taught by Liao, so as to obtain a device with an alternative conductive pathways.
Claims 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Zhai, Xu and FONG as applied to claim 1 above, and in further view of NISHIDA (US PUB. 2019/0252361).
Regarding claims 25-26, the combination of Zhai, Xu and FONG is silent on the 3DIC of claim 1, wherein the interconnect network layer has at least one lateral dimension greater than 3.3 cm (claim 25); and wherein both lateral dimensions of the interconnect network layer are greater than 2.6 cm (claim 26). However, the Examiner understands that said claim feature would have been obvious and within the ordinary skill in the art. For instance, NISHIDA teaches wherein an interconnect network layer (e.g. interposer) has at least one lateral dimension greater than 3.3 cm (Para [0048]); and wherein both lateral dimensions of the interconnect network layer are greater than 2.6 cm (Para [0048]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Response to Arguments
Applicant’s arguments with respect to claims 1-3 & 5-31 have been considered but are moot in light of new grounds of rejection. With respect to claim 1, applicant argues that the secondary reference, Xu’s redistribution structure 118 (Fig. 1B) is a metal line with a thickness of 3 to 4 microns (Page 9 of Remarks). The Examiner respectfully disagrees and directs applicant’s attention to column 4, lines 19-25, where Xu expressly teaches that the redistribution structure 118 can comprise more than one meal layer or perhaps multiple metal layers. Xu appears to refer to the overall thickness of the redistribution structure being 3 to 4 microns, and the redistribution structure can comprise multiple metal layers. It is further understood that the metal/conductive layers/lines within a redistribution structure are separated by insulating layers (e.g. see Zhai’s redistribution 130/interconnect network layer). Therefore, Xu’s redistribution structure that includes at least more than one metal layer have a thickness of 3 micron to 4 micron.
Additionally, these claim dimensions would have been obvious to one of the ordinary skill in the art in view of Xu. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a thickness of 3-4 microns for the redistribution layer or interconnect network layer.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
As such, the argument is not fund to be persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818