DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-13 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected method invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 18, 2026.
Applicant's election with traverse of Invention 1 in the reply filed on May 18, 2026 is acknowledged. The traversal is on the grounds that there is overlapping subject matter. This is found persuasive and the examiner withdraws the restriction of claims 14-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sano et al. (2022/0285320, hereafter Sano).
Regarding claim 1, Sano discloses a semiconductor device assembly, comprising: a redistribution layer (100, Fig. 1, par. 0038) having a first side and a second side opposite the first side; a first semiconductor die (200, Fig. 1, par. 0038) electrically coupled with the redistribution layer at the first side through first conductive structures (210, Fig. 1, par. 0038); and a stack of semiconductor dies (S2, Fig. 1, par. 0038) mounted on the first semiconductor die and electrically coupled with the redistribution layer, the stack of semiconductor dies including: a base semiconductor die (50U, Fig. 1, par. 0045) mounted on the first semiconductor die and electrically coupled with the redistribution layer at the first side through second conductive structures (70, Fig. 1, par. 0038); and one or more wires (17, Fig. 18, par. 0160) electrically coupling respective semiconductor dies of the stack of semiconductor dies.
Regarding claim 2, Sano discloses a semiconductor device assembly wherein: each semiconductor die of the stack of semiconductor dies (S2, Fig. 1, par. 0038) includes an active side (F50a, Fig. 1, par. 0047) and a back side (F50b, Fig. 1, par. 0047) opposite the active side; and the stack of semiconductor dies is mounted on the first semiconductor die (200, Fig. 1, par. 0038) such that the active side of each semiconductor die of the stack of semiconductor dies faces the redistribution layer (100, Fig. 1, par. 0038).
Regarding claim 3, Sano discloses a semiconductor device assembly wherein the first conductive structures (210, Fig. 1) or the second conductive structures (70, Fig. 1) include stud bump interconnects or pillar interconnects (par. 0038).
Regarding claim 4, Sano discloses a semiconductor device assembly wherein the redistribution layer (100, Fig. 1) includes polyimide (par. 0075).
Regarding claim 5, Sano discloses a semiconductor device assembly further comprising a mold (90, Fig. 1, par. 0038) disposed around the first semiconductor die (200, Fig. 1, par. 0038), the stack of semiconductor dies (S2, Fig. 1, par. 0038), the first conductive structures (210, Fig. 10, par. 0038), and the second conductive structures (70, Fig. 1, par. 0038), wherein the redistribution layer (100, Fig. 1, par. 0038) is in contact with the mold.
Regarding claim 6, Sano discloses a semiconductor device assembly further comprising a substrate (2, Fig. 12, par. 0062) adhered directly to a topmost semiconductor die (50, Fig. 12, par. 0062) in the stack of semiconductor dies (S2, Fig. 12, par. 0062).
Regarding claim 7, Sano discloses a semiconductor device assembly wherein: the first semiconductor die (200, Fig. 1) comprises a logic die (par. 0052); and the stack of semiconductor dies (50, Fig. 1) includes a stack of memory dies (par. 0047).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sano in view of Leow et al. (2023/0268327, hereafter Leow).
Regarding claim 14, Sano discloses a semiconductor device assembly, comprising: a redistribution layer (100, Fig. 1, par. 0038) having a first side and a second side opposite the first side; a first semiconductor die (200, Fig. 1, par. 0038) electrically coupled with the redistribution layer at the first side through first interconnects (210, Fig. 1, par. 0038); a stack of semiconductor dies (S2, Fig. 1, par. 0038) mounted on the first semiconductor die such that an active side (F50a, Fig. 1, par. 0047) of each semiconductor die of the stack of semiconductor dies faces the redistribution layer, the stack of semiconductor dies including: a base semiconductor die (50U, Fig. 1, par. 0038) mounted on the first semiconductor die and electrically coupled with the redistribution layer at the first side through second interconnects (70, Fig. 1, par. 0038); and one or more wires (17, Fig. 18, par. 0160) electrically coupling respective semiconductor dies of the stack of semiconductor dies; and an additional stack of semiconductor dies (S1, Fig. 1, par. 0038) mounted on and electrically coupled to the redistribution layer at the first side through third interconnects (30, Fig. 1, par. 0038) such that an active side (F10a, Fig. 1, par. 0040) of each semiconductor die of the additional stack of semiconductor dies faces the redistribution layer.
Sano fails to disclose the additional stack of semiconductor dies including one or more additional wires electrically coupling respective semiconductor dies of the additional stack of semiconductor dies.
However, Leow teaches the additional stack of semiconductor dies (125a/b/c/d, Fig. 1A, par. 0025) including one or more additional wires (130a, Fig. 1A, par. 0026) electrically coupling respective semiconductor dies of the additional stack of semiconductor dies.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sano with Leow by including wire coupling respective dies in the additional stack in order to allow universal communication while minimizing physical space.
Regarding claim 15, Sano fails to disclose a semiconductor device assembly wherein: the stack of semiconductor dies comprises memory dies of a first type; and the additional stack of semiconductor dies comprises memory dies of a second type different from the first type.
However, Leow teaches a semiconductor device assembly wherein: the stack of semiconductor dies (325, Fig. 3) comprises memory dies of a first type (par. 0041); and the additional stack of semiconductor dies (370, Fig. 3) comprises memory dies of a second type different from the first type (par. 0041).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sano with Leow by implementing stacks with a different memory type in order to optimize performance by implementing multiple modes of memory execution.
Regarding claim 16, Sano fails to disclose a semiconductor device assembly wherein: the stack of semiconductor dies comprises one of: dynamic random-access memory (DRAM) dies and NOT-AND (NAND) dies; and the additional stack of semiconductor dies comprises another of: DRAM dies and NAND dies.
However, Leow teaches a semiconductor device assembly wherein: the stack of semiconductor dies comprises (325, Fig. 3) one of: dynamic random-access memory (DRAM) dies and NOT-AND (NAND) dies (par. 0041); and the additional stack of semiconductor dies (370, Fig. 3) comprises another of: DRAM dies and NAND dies (par. 0041).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sano with Leow by implementing stacks with different memory types, DRAM and NAND, in order to optimize performance by utilizing active data processing alongside the capacity for permanent storage.
Regarding claim 17, Sano discloses a semiconductor device assembly wherein the first interconnects (210, Fig. 1), the second interconnects (70, Fig. 1), or the third interconnects (30, Fig. 1) comprise stud bump interconnects or conductive pillar interconnects (par. 0038).
Regarding claim 18, Sano fails to disclose a semiconductor device assembly wherein: the stack of semiconductor dies is shingled along a first direction; and the additional stack of semiconductor dies is shingled along a second direction different from the first direction.
However, Leow teaches a semiconductor device assembly wherein: the stack of semiconductor dies is shingled along a first direction (225, Figs. 4A, 4B, 5A; par. 0032); and the additional stack of semiconductor dies is shingled along a second direction different from the first direction (325, Figs. 4A, 4B, 5A; par. 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sano with Leow by providing stacks shingled in different directions in order to allow efficient connection without blocking access between chips, thus maximizing perimeter for wiring.
Regarding claim 19, Sano discloses a semiconductor device assembly further comprising a mold (90, Fig. 1, par. 0038) disposed around the first semiconductor die, the stack of semiconductor dies, the additional stack of semiconductor dies, the first interconnects, the second interconnects, and the third interconnects, wherein the redistribution layer is in contact with the mold.
Regarding claim 20, Sano discloses a semiconductor device assembly further comprising a substrate (2, Fig. 12, par. 0062) adhered directly to a topmost semiconductor die (50, Fig. 12) in the stack of semiconductor dies (S2, Fig. 12) and an additional topmost semiconductor die (10, Fig. 12) in the additional stack of semiconductor dies (S1, Fig. 12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shin (20220045010), in reference to claims in general;
Huang (10276545), in reference to claims in general.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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