DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Seven (7) sheets of drawings were filed on January 09, 2024.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. The drawings do not illustrate certain essential features of the claimed invention that are capable of being shown. In particular, claims 17 and 18 recite a “tip end”” at the end surface of the silicon tip, yet the drawing fails to show the “tip end” is shaped, even though these optical interfaces are central to the claimed system configuration and are capable of being illustrated.
Therefore, the, tip end must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become
aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims
the examiner presumes that the subject matter of the various claims was commonly owned as of the
effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is
advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of
each claim that was not commonly owned as of the effective filing date of the later invention in
order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35
U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claims 1, 7-8-9, 13, and 19 -20 are objected to because of the following informalities:
Regarding claim 1, lines 9 and 11, replace “is” with “are”.
Regarding claim 7, lines 6 and 8, replace “is” with “are”.
Regarding claim 8, line 2, replace “is” with “are”.
Regarding claim 9, line 2, replace “is” with “are”.
Regarding claim 13, lines 11 and 12, replace “is” with “are”.
Regarding claim 17, remove “is” after “tip end”.
Regarding claim 19, line 2, replace “is” with “are”.
Regarding claim 20, line 2, replace “is” with “are”.
Appropriate correction is required.
Applicant’s cooperation is requested in correcting any errors of which applicant may become
aware in the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17, the claim recites “the silicon tip has a tip end is at an end surface of the silicon tip, and the end surface is a surface except for the sidewalls.” This phrasing is ambiguous and fails to provide a clear boundary of the claimed invention. Specifically, it is unclear what structural limitations are intended to be defined by a surface defined solely by the exclusion of the sidewalls, as the specification and drawings lack support and fail to illustrate or describe this specific geometry. For the purposes of examination, the “the end surface” will be interpreted as a surface at the end of an optical waveguide.
Claim 18 is rejected for inheriting the indefiniteness of claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel et al. (US7118682B2), hereafter Patel.
Regarding claim 1, Patel discloses A semiconductor device for optical signal transmitting (Abstract: Structure for reducing optical signal loss), comprising: a substrate having a surface (FIG. 7. Dielectric layer); and a silicon structure (Polysilicon waveguiding structure 40), formed on the surface of the substrate (FIG. 7), wherein the silicon structure comprises an upper surface, a lower surface, and side surfaces between the upper surface and the lower surface, the lower surface is in contact with the surface of the substrate(FIG. 7 and annotated FIG. 7 below), and a plurality of first intermediate surfaces between the lower surface and the side surfaces (rounded bottom edges 46 and 48), a plurality of second intermediate surfaces between the upper surface and the side surfaces (rounded upper edges 42 and 44), the plurality of first intermediate surfaces is formed at different angles than the side surfaces, and the plurality of second intermediate surfaces is formed at different angles than the side surfaces (FIG. 7 and annotated FIG. 7 below).
Regarding claim 2, Patel discloses the device of claim 1. Patel further discloses the plurality of first intermediate surfaces (rounded bottom edges 46 and 48) are flat surfaces, convex surfaces, concave surfaces, or a combination thereof (FIG. 7 and annotated FIG. 7 below).
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Regarding claim 3, Patel discloses the device of claim 1. Patel further discloses the plurality of second intermediate surfaces (rounded bottom edges 46 and 48) are flat surfaces, convex surfaces, concave surfaces, or a combination thereof (FIG. 7 and annotated FIG. 7 below).
Regarding claim 4, Patel discloses the device of claim 1. Patel further discloses an oxide layer covering the silicon structure (FIG. 17 Oxide layer 70).
Regarding claim 5, Patel discloses the device of claim 1. Patel further discloses the substrate (Dielectric layer 3) is an oxide layer or a SOI substrate (Column 6 lines 62-65).
Regarding claim 6, Patel discloses the device of claim 1. Patel further discloses the silicon structure is single crystal silicon, polysilicon, or amorphous silicon (Column 6 lines 8-11).
Regarding claim 7, Patel discloses a semiconductor device for optical signal transmitting (Abstract: Structure for reducing optical signal loss), comprising: a substrate having a surface (FIG. 7. Dielectric layer); and a silicon tip (Polysilicon waveguiding structure 40), formed on the surface of the substrate (FIG. 7), wherein the silicon tip comprises an upper portion, a lower portion, and sidewalls extending from the upper portion to the lower portion (FIG. 7 and annotated FIG. 7 below), wherein a plurality of first edges (rounded bottom edges 46 and 48) between the lower portion and the sidewalls is, in a cross-section view, a rounded edge or a sloping edge formed at different angles than the sidewalls (FIG. 7), and a plurality of second edges between the upper portion (Rounded upper edges 42 and 44) and the sidewalls are, in the cross-section view, a rounded edge or a sloping edge formed at different angles than the sidewalls (FIG. 7).
Regarding claim 8, Patel discloses the device of claim 7. Patel further discloses the plurality of first edges are the rounded edge (rounded bottom edges 46 and 48), and the plurality of second edges (Rounded upper edges 42 and 44) are the rounded edge (FIG. 7).
Regarding claim 10, Patel discloses the device of claim 7. Patel further discloses an oxide layer covering the silicon tip (FIG. 17 Oxide layer 70).
Regarding claim 11, Patel discloses the device of claim 7. Patel further discloses the substrate (Dielectric layer 3) is an oxide layer or a SOI substrate (Column 6 lines 62-65).
Regarding claim 12, Patel discloses the device of claim 7. Patel further discloses the silicon tip is single crystal silicon, polysilicon, or amorphous silicon (Column 6 lines 8-11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Patel et 140al. (US7118682B2), hereafter Patel, in view of Wang et al. (Double-tip Scandium Aluminum Nitride Edge Couplers), hereafter Wang.
Regarding claim 9, Patel discloses the device of claim 7. Patel further discloses the plurality of first and second edges (rounded bottom edges 46 and 48 and rounded upper edges 42 and 44). Patel fails to disclose the edges are sloped.
Wang discloses sloped edges of a waveguide (FIG. 1b).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify Patel’s device to include sloped edges, as this represents routine optimization. Adjusting the edge geometry to achieve a desired fit or optical performance is merely a matter of routine design choice.
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Patel et al. (US7118682B2), hereafter Patel, in view of Gambino et al. (US9715064B1), hereafter Gambino.
Regarding claim 13, Patel discloses a system for optical signal processing (Abstract: Structure for reducing optical signal loss), comprising: a semiconductor device configured to transmit one or more optical signals (Abstract: Structure for reducing optical signal loss) using a light beam (Optical waveguide or signal processor inherently involve light beams); wherein the semiconductor device comprising: a substrate having a surface (FIG. 7. Dielectric layer); and a silicon tip (Polysilicon waveguiding structure 40), formed on the surface of the substrate (FIG. 7), wherein the silicon tip comprises an upper portion, a lower portion, and sidewalls extending from the upper portion to the lower portion (FIG. 7 and annotated FIG. 7 below), wherein a plurality of first edges (rounded bottom edges 46 and 48) between the lower portion and the sidewalls are, in a cross-section view, a rounded edge or a sloping edge formed at different angles than the sidewalls (FIG. 7), and a plurality of second edges between the upper portion (Rounded upper edges 42 and 44) and the sidewalls are. in the cross-section view, a rounded edge or a sloping edge formed at different angles than the sidewalls (FIG. 7).
Patel fails to disclose a photonic die configured to receive the light beam for processing the one or more optical signals.
Gambino discloses a photonic die (FIG 1A) configured to receive the light beam for processing the one or more optical signals (Column 7 lines 25-28). Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to integrate the optical signal processing semiconductor device of Patel with a photonic die, such as the one taught by Gambino. A person of ordinary skill in the art would have been motivated to combine these teachings in order to enable high -speed routing and signal processing capabilities in a single co-packaged optical (CPO) assembly or system. By coupling Patel's semiconductor waveguide/transmission device with a separate or adjacent photonic die, the artisan would achieve improved optical-to-electrical signal conversion and efficient light beam processing. Implementing this combination would only require applying standard photonic integration techniques and routine chip-to-chip or die-to-die optical coupling methods, resulting in a unified semiconductor package with a reasonable expectation of success.
Regarding claim 14, Patel/ Gambino discloses the device of claim 13. Patel further discloses a silicon tip (Polysilicon waveguiding structure 40). Patel fails to disclose the photonic die comprises a first waveguide and a grating coupler for coupling the light beam from the silicon tip of the semiconductor device.
Gambino teaches the photonic die comprises a first waveguide (waveguide 112) and a grating coupler (grating coupler 113) for coupling the light beam from the waveguide (122).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the silicon waveguide of Patel with the waveguide of Gambino to achieve optical. Optical signals propagating through semiconductor-on-insulator (SOI) structures with right-angled corners suffer from intensity spikes, which lead to significant optical signal loss. A person of ordinary skill in the art would look to known CMOS processing techniques to round the right-angled edges of the silicon waveguiding structure to reduce optical field intensity and decrease signal loss.
Regarding claim 15, Patel/ Gambino discloses the device of claim 13. Patel further discloses a silicon tip (Polysilicon waveguiding structure 40). Patel fails to disclose the grating coupler is disposed over the upper portion of the silicon tip.
Gambino teaches the grating coupler (grating coupler 113) is disposed over the upper portion (FIG. 1A) of the waveguide 122.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the silicon waveguide (Column 2 lines 42-50)) of Patel with the waveguide of Gambino (122) to achieve optical coupling. Optical signals propagating through semiconductor-on-insulator (SOI) structures with right-angled corners suffer from intensity spikes, which lead to significant optical signal loss. A person of ordinary skill in the art would look to known CMOS processing techniques to round the right-angled edges of the silicon waveguiding structure to reduce optical field intensity and decrease signal loss.
Regarding claim 16, Patel/ Gambino discloses the device of claim 13. Patel fails to disclose a photonic die comprising a second waveguide configured for edge coupling.
Gambino teaches a photonic die (FIG. 1A) comprising a second waveguide(127).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to integrate the device of Patel with a photonic die featuring a second waveguide, such as the one taught by Gambino. The modification represents a predictable design choice to enable edge coupling, a standard technique in optical routing and integration. Integrating a second waveguide onto a photonic die is a predictable modification for achieving improved signal routing and managing optical power.
Patel/Gambino fails to teach the second waveguide is an edge coupler.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the device of Patel/Gambino to include a second waveguide that is an edge coupler based on known coupling methods. Modifying a waveguide to be an edge coupler is a simple matter of selecting a known, standard coupling method (such as a grating coupler, spot-size converter, or tapered waveguide) to achieve efficient on-chip light injection or extraction. Replacing the terminal end of Patel/Gambino second waveguide with an edge coupler yields predictable results, improving coupling efficiency without fundamentally altering the core operating principles of the waveguide.
Regarding claim 17, Patel/Gambino discloses the device of claim 16. Patel further discloses the silicon tip (Polysilicon waveguiding structure 40 has a tip end (the tip of the waveguide necessarily has a tip end) at an end surface of the silicon tip (FIG. 7), and the end surface is a surface (the surface annotated as upper surface below) except for the sidewalls.
Regarding claim 18, Patel/Gambino/Huang discloses the device of clam 17. Patel further discloses a tip end (the tip of the waveguide necessarily has a tip end). Patel fails to teach the tip end is configured to align with the second waveguide of the photonic die.
Gambino teaches a first (127) and second waveguide (122), wherein the tip end of the optical fiber (190) is configured to align with the second waveguide(FIG. 1A and 1B).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to integrate the device of Patel with a photonic die featuring a second waveguide, such as the one taught by Gambino. The modification represents a predictable design choice to enable edge coupling, a standard technique in optical routing and integration. Integrating a second waveguide onto a photonic die is a predictable modification for achieving improved signal routing and managing optical power.
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Regarding claim 19, Patel/ Gambino discloses the device of claim 13. Patel further discloses the plurality of first edges is the rounded edge (rounded bottom edges 46 and 48), and the plurality of second edges (Rounded upper edges 42 and 44) is the rounded edge (FIG. 7).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Patel et al. (US7118682B2), hereafter Patel, in view of Gambino et al. (US9715064B1), hereafter Gambino, and in further view of Wang et al. (Double-tip Scandium Aluminum Nitride Edge Couplers), hereafter Wang.
Regarding claim 20, Patel/Gambino discloses the device of claim 7. Patel further discloses the plurality of first and second edges(rounded bottom edges 46 and 48 and rounded upper edges 42 and 44). Patel/Gambino fails to disclose the edges are sloped.
Wang discloses sloped edges of a waveguide (FIG. 1b).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify Patel/Gambino’s device to include sloped edges, as this represents routine optimization. Adjusting the edge geometry to achieve a desired fit or optical performance is merely a matter of routine design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
➢ Lee et al. (US2003012493A1) see the entire disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAJANAE N GREEN whose telephone number is (571)272-2188. The examiner can normally be reached Tues-Fri. 5:30a-3:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAJANAE NICOLE GREEN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
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