Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response application 18/407480 filed on 01/09/24.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Subhasis Bose (US Pub. 2009/0254874).
As to claim 1 and 17 the prior art teaches a method for performing block level exploration of integrated circuit (IC) design, the method being applied to an electronic device, the method comprising:
running a synthesis control procedure on at least one processor within the electronic device, for performing automatic synthesis plus place and route (ASPR) of a target design of an IC, wherein the synthesis control procedure comprises: performing netlist generation to generate a first netlist for the target design of the IC (see fig 1 paragraph 0075-0080);
performing performance, power and area (PPA) configurations preparation to prepare a set of PPA-related configurations (see fig 1-3 paragraph 0255-0260);
performing macro placement generation to generate a set of macro placements corresponding to the set of PPA-related configurations (see fig 2-4 paragraph 0298-0303);
and executing synthesis processing according to the set of macro placements to generate multiple intermediate netlists, respectively, and generating multiple synthesis reports of the multiple intermediate netlists for the set of PPA-related configurations, respectively, for selectively outputting at least one intermediate netlist among the multiple intermediate netlists as at least one resultant netlist and at least one floor plan, for use of further place and route (P&R) processing (see fig 22-24 paragraph 0650-0656).
As to claim 2 the prior art teaches wherein performing the netlist generation to generate the first netlist for the target design of the IC further comprises: executing synthesis processing without referring to any predetermined physical location information regarding any part of the IC, to generate the first netlist for the target design of the IC (see fig 1-4 paragraph 0258-0265).
As to claim 3 the prior art teaches wherein performing the netlist generation to generate the first netlist for the target design of the IC further comprises:
receiving a register transfer level (RTL) code, wherein the RTL code indicates the target design of the IC (see fig 4-8 paragraph 0433-0438);
and executing synthesis processing according to the RTL code to generate the first netlist for the target design of the IC (see fig 4-8 paragraph 0436-0442).
As to claim 4 the prior art teaches wherein the set of PPA-related configurations comprise at least one performance-related configuration, at least one power-related configuration and at least one area-related configuration (see fig 1-3 paragraph 0256-0264).
As to claim 5 the prior art teaches wherein the at least one area-related configuration comprises at least one configuration of at least one area for being occupied by at least one predetermined component within the IC (see fig 1-4 paragraph 0268-0273).
As to claim 6 the prior art teaches wherein the at least one configuration of the at least one area comprises at least one configuration of one or a combination of a shape of the at least one area, an area size of the at least one area, and an aspect ratio of the at least one area (see fig 1-4 paragraph 0271-0276).
As to claim 7 and 10 the prior art teaches wherein the at least one area-related configuration further comprises at least one configuration of one or a combination of a port location of at least one port within the IC, a feedthrough port number of at least one feedthrough port within the IC, a feedthrough port location of the at least one feedthrough port, at least one routing layer within the IC, and a user-defined region for at least one module within the IC (see fig 2-5 paragraph 0275-0280).
As to claim 8, the prior art teaches wherein the at least one performance-related configuration comprises at least one configuration of at least one area for being occupied by at least one predetermined component within the IC (see fig 2-5 paragraph 0275-0280).
As to claim 9 the prior art teaches wherein the at least one configuration of the at least one area comprises at least one configuration of one or a combination of a shape of the at least one area, an area size of the at least one area, and an aspect ratio of the at least one area (see fig 3-7 paragraph 0306-0310).
As to claim 10 the prior art teaches wherein the at least one performance-related configuration further comprises at least one configuration of one or a combination of a port location of at least one port within the IC, a feedthrough port number of at least one feedthrough port within the IC, a feedthrough port location of the at least one feedthrough port, at least one routing layer within the IC, and a user-defined region for at least one module within the IC (see fig 3-8 paragraph 0310-0315).
As to claim 11 the prior art teaches wherein the at least one power-related configuration comprises at least one configuration of at least one area for being occupied by at least one predetermined component within the IC (see fig 3-8 paragraph 0344-0348).
As to claim 12 the prior art teaches wherein the at least one configuration of the at least one area comprises at least one configuration of one or a combination of a shape of the at least one area, an area size of the at least one area, and an aspect ratio of the at least one area (see fig 3-10 paragraph 0347-0351).
As to claim 13 the prior art teaches wherein the at least one power-related configuration further comprises at least one configuration of one or a combination of a port location of at least one port within the IC, and a power grid setting of at least one power grid line within the IC (see fig 6-12 paragraph 0350-0355).
As to claim 14 the prior art teaches wherein the set of PPA-related configurations comprise at least one configuration of at least one area for being occupied by at least one predetermined component within the IC (see fig 22-24 paragraph 0654-0659); and performing the macro placement generation to generate the set of macro placements corresponding to the set of PPA-related configurations further comprises: performing the macro placement generation to generate the set of macro placements corresponding to the set of PPA-related configurations for placing the at least one predetermined component (see fig 22-24 paragraph 0658-0665).
As to claim 15 the prior art teaches wherein the at least one configuration of the at least one area comprises at least one configuration of one or a combination of a shape of the at least one area, an area size of the at least one area, and an aspect ratio of the at least one area (see fig 22-26 paragraph 0670-0676).
As to claim 16 the prior art teaches wherein the electronic device is arranged to selectively output the at least one intermediate netlist among the multiple intermediate netlists as the at least one resultant netlist, for use of further P&R processing (see fig 3-8 paragraph 0410-0415).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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