Prosecution Insights
Last updated: October 02, 2026
Application No. 18/407,675

Array Of Capacitors, Array Of Memory Cells, And Methods Used In Forming An Array Of Capacitors

Non-Final OA §103
Filed
Jan 09, 2024
Priority
Jan 11, 2023 — provisional 63/438,304
Examiner
CHOU, SHIH TSUN A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
2 (Non-Final)
77%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
374 granted / 483 resolved
+9.4% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
24 currently pending
Career history
506
Total Applications
across all art units

Statute-Specific Performance

§103
51.4%
+11.4% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
26.8%
-13.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 483 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of invention I, claims 1-15, in the reply filed on 3/10/2026 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/10/2026. Drawings Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. Claim Objections Claim 1 is objected to because of the following informalities: the text “a top and bottom of the sacrificial material” in lines 4-5 is suggested to be changed to “a top surface and a bottom surface of the sacrificial material” for clarity. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 3-4,10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 2022/0037460) in view of Bajaj (US 2022/0270870). Regarding claim 1, Lu discloses, in FIG. 2A and in related text, a method used in forming an array of capacitors, comprising: forming horizontally-spaced openings (22) into sacrificial material (202, 204) and through insulative material (203) that is between a top and bottom of the sacrificial material; the insulative material at least predominately comprising at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride; the insulative material with horizontally-spaced openings there-through comprising an insulative horizontal lattice (see Lu, FIG. 2A, [0030]-[0032]: insulative material 203 having a periodic pattern of openings 22 is considered as a lattice structure. Merriam-Webster defines a lattice as a regular geometrical arrangement of points or objects over an area or in space); depositing an insulative lining (23) within the horizontally-spaced openings and directly above the sacrificial material (202, 204), the insulative lining at least predominately comprising at least one of a silicon oxide and a silicon oxynitride (see Lu, FIG. 2B, [0031], [0033], [0049]); forming first capacitor electrodes (24) that are individually within individual of the horizontally-spaced openings laterally over the insulative lining that is in the horizontally-spaced openings (see Lu, FIG. 2D, [0036]); removing the sacrificial material (see Lu, FIG. 2H, [0045]) and forming a capacitor insulator (291) over the first capacitor electrodes and the insulative horizontal lattice (see Lu, FIG. 2J, [0055]-[0058]); and forming second-capacitor-electrode material (30) over the capacitor insulator (see Lu, FIG. 2K, [0057]). Lu discloses that the insulative lining (23) of silicon oxide is deposited with an atomic layer deposition process (see Lu, [0034]). Lu does not explicitly disclose during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma. Bajaj teaches depositing silicon oxide layer with atomic layer deposition cycles including a nitrogen-containing plasma step as part of each cycle (see Bajaj, FIG. 3, [0040]-[0044]). Thus, Bajaj together with Lu teaches during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma. Lu and Bajaj are analogous art because they both are directed to semiconductor device and manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu with the features of Bajaj because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lu to include during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma, as taught by Bajaj, to providing resulting films with improved qualities, conformality and good electrical properties (see Bajaj, [0023]). Regarding claim 3, Lu in view of Bajaj teaches the method of claim 1. Bajaj teaches wherein the nitrogen-containing plasma is derived from at least one of N2, NH3, NF3, and NOx, with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1. Regarding claim 4, Lu in view of Bajaj teaches the method of claim 1. Lu discloses wherein the insulative material and the insulative horizontal lattice (203) at least predominately comprise the silicon nitride (see discussion on claim 1 above). Regarding claim 10, Lu in view of Bajaj teaches the method of claim 1. Lu discloses wherein the insulative lining at least predominately comprises the silicon oxide (see discussion on claim 1 above). Regarding claim 13, Lu in view of Bajaj teaches the method of claim 1. Lu discloses wherein the insulative lining (23) is deposited aside the insulative horizontal lattice (203) (see Lu, FIG. 2B, [0033]-[0034]). Regarding claim 14, Lu in view of Bajaj teaches the method of claim 1. Lu discloses removing all of the insulative lining (see Lu, FIG. 2H, [0045]) prior to forming the capacitor insulator (see Lu, FIG. 2J, [0055]-[0058]). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Bajaj, and further in view of Austin (US 2023/0175117). Regarding claim 11, Lu in view of Bajaj teaches the method of claim 1. Lu discloses wherein the insulating lining (23) is silicon nitride (see discussion on claim 1 above). Lu does not explicitly disclose wherein the insulative lining at least predominately comprises the silicon oxynitride. Austin teaches insulating lining of silicon oxide such as silicon oxynitride (see Austin, [0033]). Austin teaches wherein the insulative lining at least predominately comprises the silicon oxynitride. Lu and Austin are analogous art because they both are directed to semiconductor device and manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu with the features of Austin because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lu to include wherein the insulative lining at least predominately comprises the silicon oxynitride, as taught by Austin, to provide a protective liner (see Austin, [0033]), and because it is simple substitution of one known element for another to obtain predictable results (as liner materials) (see MPEP § 2143). Claims 1, 4-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (US 2023/0320061) in view of Bajaj (US 2022/0270870). Regarding claim 1, Suh discloses, in FIG. 4C and in related text, a method used in forming an array of capacitors, comprising: forming horizontally-spaced openings (VH) into sacrificial material (131, 133, 135) and through insulative material (132, 134) that is between a top and bottom of the sacrificial material; the insulative material at least predominately comprising at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride; the insulative material with horizontally-spaced openings there-through comprising an insulative horizontal lattice (see Suh, FIG. 4C, [0041]-[0044], insulative material 132, 134 having a periodic pattern of openings VH is considered as a lattice structure. Merriam-Webster defines a lattice as a regular geometrical arrangement of points or objects over an area or in space); depositing an insulative lining (150) within the horizontally-spaced openings (VH) and directly above the sacrificial material (131, 133, 135), the insulative lining at least predominately comprising at least one of a silicon oxide and a silicon oxynitride (see Suh, FIG. 4F, [0054]); forming first capacitor electrodes (LE) that are individually within individual of the horizontally-spaced openings laterally over the insulative lining (150P) that is in the horizontally-spaced openings (see Suh, FIG. 4H, [0064]); removing the sacrificial material (see Suh, FIG. 4I, [0067]-[0068]) and forming a capacitor insulator (170) over the first capacitor electrodes (LE) and the insulative horizontal lattice (132P, 134P) (see Suh, FIG. 4J, [0069]); and forming second-capacitor-electrode material (UE) over the capacitor insulator (170) (see Suh, FIG. 4K [0071]). Suh discloses depositing the insulative lining of silicon oxide. Suh does not explicitly disclose during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma. Bajaj teaches depositing silicon oxide layer with atomic layer deposition cycles including a nitrogen-containing plasma step as part of each cycle (see Bajaj, FIG. 3, [0040]-[0044]). Thus, Bajaj together with Suh teaches during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma. Suh and Bajaj are analogous art because they both are directed to semiconductor device and manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Suh with the features of Bajaj because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Suh to include during the depositing, intermittently exposing the insulative lining to a nitrogen-containing plasma, as taught by Bajaj, to providing resulting films with improved qualities, conformality and good electrical properties (see Bajaj, [0023]). Regarding claim 4, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately comprise the silicon nitride (see Suh, [0042]). Regarding claim 5, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately comprise the silicon boronitride (see Suh, [0042]) Regarding claim 6, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately comprise the silicon carbonitride (see Suh, [0042]). Regarding claim 7, Suh in view of Bajaj teaches the method of claim 6. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately is silicon carbonitride (see Suh, [0042]), that is, carbon content in the silicon carbonitride has non-zero atomic percent. Suh does not explicitly disclose wherein carbon content in the silicon carbonitride is 0.1 atomic percent to 30.0 atomic percent. However, the limitation would have been found obvious since generally, differences in concentration will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See also, MPEP § 2144.05. Regarding claim 8, Suh in view of Bajaj teaches the method of claim 7. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately is silicon carbonitride (see Suh, [0042]), that is, carbon content in the silicon carbonitride has non-zero atomic percent. Suh does not explicitly disclose wherein carbon content in the silicon carbonitride is 5.0 atomic percent to 7.0 atomic percent. However, the limitation would have been found obvious since generally, differences in concentration will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See also, MPEP § 2144.05. Regarding claim 9, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative material and the insulative horizontal lattice (132, 134) at least predominately comprise at least two of the silicon nitride, the silicon boronitride, and the silicon carbonitride (see Suh, [0042]). Regarding claim 10, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative lining (150) at least predominately comprises the silicon oxide (see discussion on claim 1 above). Regarding claim 12, Suh in view of Bajaj teaches the method of claim 1. Suh discloses wherein the insulative lining (150) is not deposited aside the insulative horizontal lattice (132, 134) (see Suh, FIG. 4F, [0054]). Allowable Subject Matter Claims 2 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the objection(s) set forth in this Office Action, and in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of records, individually or in combination, do not disclose nor teach “wherein the intermittently exposing results in less of the insulative lining being deposited directly above the sacrificial material than would otherwise occur under identical depositing conditions but for the intermittently exposing” in combination with other limitations as recited in claim 2. The prior art of records, individually or in combination, do not disclose nor teach “wherein the insulative horizontal lattice comprises carbon; the insulative horizontal lattice having less carbon, if any, immediately-laterally-adjacent individual of the first capacitor electrodes than laterally-distal therefrom” in combination with other limitations as recited in claim 15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jan 09, 2024
Application Filed
Jul 09, 2026
Non-Final Rejection (signed) — §103
Sep 08, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
77%
Grant Probability
94%
With Interview (+16.4%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 483 resolved cases by this examiner. Grant probability derived from career allowance rate.

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