DETAILED ACTION
This Office Action is responsive to the Applicant’s communications filed 9 January 2024 and 12 March 2026. In view of these communications, claims 1-28 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 12-21 were withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12 March 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 recites the limitations of first and second build-up layers in lines 4 and 9 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the sake of the present examination, claim 11 will be interpreted as depending from claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakaguchi et al. (JP 2010114187 A), hereinafter referred to as Sakaguchi et al.
Regarding claim 1, Sakaguchi et al. teaches a printed circuit board comprising:
a core layer (21) (see page 7, third-to-last paragraph: substrate body 21) including an inorganic insulating layer (page 8, second paragraph: substrate body 21 is glass), a resin layer (39) covering at least a portion of an external side surface of the inorganic insulating layer (21) (page 9, third-to-last paragraph: resin 39 provided so as to cover the peripheral side surface of substrate body 21), and a second insulating layer (23) (page 7, third-to-last paragraph and page 8, fifth paragraph: insulating film 23 covering the lower surface of the substrate 21) covering at least a portion of a lower surface of each of the inorganic insulating layer (21) and the resin layer (39) and having an interlayer boundary with the resin layer (39) (see page 8, fifth paragraph and Fig. 3);
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a first wiring layer (28, 29) disposed on an upper surface of the core layer (21) (page 8, paragraphs 7-8: wiring pattern 28, 29 provided on the upper surface of insulating layer 22); and
a second wiring layer (31, 32) disposed on a lower surface of the core layer (21) (page 8, paragraphs 9 and 11: wiring patterns 31, 32 formed on insulating layer 23),
wherein the external side surface of the inorganic insulating layer (21) is substantially perpendicular to at least one of the upper surface and the lower surface of the inorganic insulating layer (21) (Fig. 3 and page 7, final paragraph: the substrate 21 is formed in a plate, or rectangular, shape).
Regarding claim 2, Sakaguchi et al. teaches the printed circuit board according to claim 1, wherein the core layer (21) further includes a first insulating layer (22) covering at least a portion of an upper surface of each of the inorganic insulating layer (21) and the resin layer (39) and having an interlayer boundary with the resin layer (39) (see page 8, paragraph 4: insulating film 22 formed separately from resin layer 39 is formed to cover the upper surface of substrate body 21).
Regarding claim 3, Sakaguchi et al. teaches the printed circuit board according to claim 2, wherein the upper surface and the lower surface of the inorganic insulating layer (21) are substantially coplanar with the upper surface and the lower surface of the resin layer (39) (see Figs. 3 and 14 and page 10, paragraph 6: the resin 39 is formed in a notch 38 that is cut through substrate 21; page 11, paragraphs 2-5 describe the forming of the notch 38 such that it is coplanar with the surface of board 21).
Regarding claim 4, Sakaguchi et al. teaches the printed circuit board according to claim 2, wherein the resin layer (39) includes an organic insulating material different from those of the first and second insulating layers (22, 23) (page 8, paragraphs 4-5: insulating layers 22, 23 are a SiO film; page 10, first paragraph: resin 39 is an epoxy, polyimide, or silicone resin).
Regarding claim 8, Sakaguchi et al. teaches the printed circuit board according to claim 1, wherein the inorganic insulating layer (21) includes a glass layer or a silicon layer (page 8, second paragraph: the material of insulating body 21 is silicon or glass).
Claim(s) 22-23 and 25-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanda (US 20070009718 A1), hereinafter referred to as Kanda.
Regarding claim 22, Kanda teaches a printed circuit board comprising:
an insulating body (100) in which a glass layer (110) is embedded, and including a plurality of insulating layers (152d) disposed on and below the glass layer (Fig. 1, paragraph 36: core 110 sandwiched by build-up layers 140, which are comprised of insulating layers 152d; paragraph 49: the core layer 110 may be a glass epoxy resin layer);
a plurality of wiring layers (152a) embedded in the insulating body (100) and disposed on and below the glass layer (110) (Fig. 1, paragraph 36: build-up layers 140 include wiring layers 152a and the wiring layers 117 closest to the core layer 110); and
a plurality of via layers (152c) embedded in the insulating layer (152d) and the glass layer (110) to connect the plurality of wiring layers (152a) on different levels to each other (Fig. 1, paragraph 36: the wiring layers 152a are connected to each other by via layers 152c and a via through the core layer 110 which is omitted in Fig. 1 but can be seen in Figs. 3 and 7),
wherein a material of the insulating body (160) in contact with a side surface of the glass layer (110) and a material of the insulating body (152d) in contact with an upper surface or a lower surface of the glass layer are different from each other (paragraph 65: layers 152d of buildup layers 140 are a glass cloth layer; paragraph 85: the edge layer 160 may comprise a simple epoxy resin without the glass filler).
Regarding claim 23, Kanda teaches the printed circuit board according to claim 22 wherein the material of the insulating body in contact with the side surface of the glass layer includes a resin layer comprising an underfill or an epoxy molding compound (EMC) (see paragraph 85: the resin of edge layer 160 may comprise an underfill).
Regarding claim 25, Kanda teaches the printed circuit board according to claim 22, wherein a through-via (115), among the plurality of via layers, penetrates through the glass layer (110) and is connected to another via (152c) among the plurality of via layers (152c) (Figs. 1 and 3; paragraphs 36 and 46: core layer 110 comprises conductive part 115, connected to the vias 152c of the buildup layers 140).
Regarding claim 26, Kanda teaches the printed circuit board according to claim 22, wherein vias (152c), among the plurality of via layers (152c), disposed on or below the glass layer (110), have a tapered structure tapered in a direction toward the glass layer (110) (see Fig. 1 and Figs. 8A-8F).
Regarding claim 27, Kanda teaches the printed circuit board according to wherein the number of wiring layers (152d) among the plurality of wiring layers (152d) disposed on the glass layer (110) is different the number of wiring layers (152d) among the plurality of wiring layers (152d) disposed below the glass layer (110) (paragraphs 63 and 70: the number of buildup layers 140 is adjustable depending on the need of the designers).
Regarding claim 28, Kanda teaches the printed circuit board according to wherein the number of wiring layers (152d) among the plurality of wiring layers (152d) disposed on the glass layer (110) is the same as the number of wiring layers (152d) among the plurality of wiring layers (152d) disposed below the glass layer (110) (Fig. 1 and paragraphs 63 and 70: the number of buildup layers 140 is adjustable depending on the need of the designers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5-7 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakaguchi et al. in view of Kanda.
Regarding claim 5, Sakaguchi et al. teaches the printed circuit board according to claim 2, further comprising:
a through-via (25, 26) configured to penetrate through the inorganic insulating layer (21) (page 13, paragraph 4: through electrodes 25 and 26); and
a first connection via (26A) configured to penetrate through the first insulating layer (22), connected to the first wiring layer (28, 29), and coming into contact with an upper surface of the through-via (25, 26) (Fig. 3: upper portion of the vias 25, 26 are formed in the insulating layer 22),
a second connection via (51, 52) configured to penetrate through the second insulating layer (23), connected to the second wiring layer (31, 32), and coming into contact with a lower surface of the through-via (25, 26) (see Fig. 3 and page 13, third paragraph).
Sakaguchi et al. does not teach that the first and second connection vias are tapered in opposite directions. Kanda does teach that the first and second connection vias may be tapered in opposite directions (see Kanda Fig. 1 and Figs. 8A-8F).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first and second connection vias of Sakaguchi et al. in tapered shapes as taught by Kanda because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1976).
Regarding claim 6, Sakaguchi et al. teaches the printed circuit board according to claim 1, but does not teach that the resin layer is disposed to extend to cover at least a portion of the upper surface of the inorganic insulating layer.
Kanda does teach that the resin layer is disposed to extend to cover at least a portion of the upper surface of the inorganic insulating layer (see Kanda Fig. 16D and paragraph 115: the core layer 110 extends beyond the buildup layers 140 such that the upper surface of the core layer 110 is covered by the edge layer 160).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin layer such that it covers at least a portion of the upper surface of the inorganic insulating layer as taught by Kanda because such an arrangement can reduce the shearing stress on the core layer and prevent cracks in the core layer (Kanda paragraph 115).
Regarding claim 7, Sakaguchi et al. teaches the printed circuit board according to claim 6, further comprising:
a through-via (25, 26) configured to penetrate through the inorganic insulating layer (21) (page 13, paragraph 4: through electrodes 25 and 26); and
a first connection via (26A) configured to penetrate through the first insulating layer (22), connected to the first wiring layer (28, 29), and coming into contact with an upper surface of the through-via (25, 26) (Fig. 3: upper portion of the vias 25, 26 are formed in the insulating layer 22),
a second connection via (51, 52) configured to penetrate through the second insulating layer (23), connected to the second wiring layer (31, 32), and coming into contact with a lower surface of the through-via (25, 26) (see Fig. 3 and page 13, third paragraph).
Sakaguchi et al. does not teach that the first and second connection vias are tapered in opposite directions. Kanda does teach that the first and second connection vias may be tapered in opposite directions (see Kanda Fig. 1 and Figs. 8A-8F).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first and second connection vias of Sakaguchi et al. in tapered shapes as taught by Kanda because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1976).
Regarding claim 9, Sakaguchi et al. teaches the printed circuit board according to claim 1, but does not teach one or more first build-up insulating layers disposed on the upper surface of the core layer and configured to cover the first wiring layer; one or more first build-up wiring layers disposed on or in the one or more first build-up insulating layers; one or more first build-up via layers each penetrating through at least one of the one or more first build-up insulating layers; one or more second build-up insulating layers disposed on the lower surface of the core layer and configured to cover the second wiring layer; one or more second build-up wiring layers disposed on or in the one or more second build-up insulating layers; and one or more second build-up via layers each penetrating through at least one of the one or more second build-up insulating layers, wherein the one or more first and second build-up via layers are tapered in opposite directions.
Kanda does teach one or more first build-up insulating layers (140) disposed on the upper surface of the core layer (110) and configured to cover the first wiring layer (117) (Fig. 1, paragraph 36: core 110 and first wiring layer 117 sandwiched by build-up layers 140);
one or more first build-up wiring layers (152a) disposed on or in the one or more first build-up insulating layers (140) (Fig. 1, paragraph 36: build-up layers 140 are comprised of wiring layers 152a);
one or more first build-up via layers (152c) each penetrating through at least one of the one or more first build-up insulating layers (140) (Fig. 1, paragraph 36: conductive parts 152a connected to each other through via 152c);
one or more second build-up insulating layers (140) disposed on the lower surface of the core layer (110) and configured to cover the second wiring layer (117) (Fig. 1, paragraph 36: core 110 and wiring layer 117 sandwiched by build-up layers 140);
one or more second build-up wiring layers (152a) disposed on or in the one or more second build-up insulating layers (140) (Fig. 1, paragraph 36: build-up layers 140 are comprised of wiring layers 152a); and
one or more second build-up via layers each penetrating through at least one of the one or more second build-up insulating layers (Fig. 1, paragraph 36: conductive parts 152a connected to each other through via 152c),
wherein the one or more first and second build-up via layers (152c) are tapered in opposite directions (see Kanda Fig. 1 and Figs 8A-8F).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the board of Sakaguchi et al. with the build-up layers as recited in the claim and taught by Kanda because the layers of Kanda enable further connections without warping and cracking problems (Kanda paragraphs 4-5).
Regarding claim 10, Sakaguchi et al. in view of Kanda teaches the printed circuit board according to claim 9, but does not teach that the one or more first build-up insulating layers have a greater number of layers than the one or more second build-up insulating layers.
Kanda does teach that the one or more first build-up insulating layers have a greater number of layers than the one or more second build-up insulating layers (paragraphs 63 and 70: the number of buildup layers 140 is adjustable depending on the need of the designers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the one or more first build-up insulating layers with a greater number of layers than the one or more second build-up insulating layers as taught by Kanda because Kanda teaches that the number of layers is adjustable depending on the needs of the designers (Kanda paragraphs 63 and 70). Further, providing additional buildup layers to one side or another would require mere duplication of essential working parts of a device, which involves only routine skill in the art. St Regis Paper Co. V. Bemis Co., 193 USPQ 8.
Regarding claim 11, Sakaguchi et al. in view of Kanda teaches the printed circuit board according to claim 8, further comprising:
a first resist layer (35) disposed on the one or more first build-up insulation layers (22) and having one or more first openings (35b) configured to respectively expose at least a portion of an uppermost first build-up wiring layer among the one or more first build-up wiring layers (Fig. 3 and page 12, paragraph 7: insulating layer 35 has openings 35b to expose the wiring layer 28, 29);
a second resist layer (36) disposed on the one or more second build-up insulation layers and having one or more second openings (36b) configured to respectively expose at least a portion of a lowermost second build-up wiring layer of the one or more second build-up wiring layers (see Fig. 3 and page 9, paragraph 6: insulating layer 36 has openings 36b to expose the wiring layer 31, 32); and
one or more semiconductor chips (12, 13) disposed on the first resist layer (35), respectively, and connected to at least a portion of the uppermost first build-up wiring layer (28, 29) exposed through the one or more first openings, respectively (Fig. 3 and page 13, paragraphs 2-3).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanda in view of Mitarai (US 20250254790 A1), hereinafter referred to as Mitarai.
Regarding claim 24, Kanda teaches the printed circuit board according to claim 22, but does not teach that the material of the insulating body in contact with the upper surface or the lower surface of the glass layer comprises at least one of an Ajinomoto build-up film (ABF), a photo imageable dielectric (PID), and a bonding sheet (BS).
Mitarai does teach that the material of the insulating body in contact with the upper surface or the lower surface of the glass layer may comprise at least one of an Ajinomoto build-up film (ABF),a photo imageable dielectric (PID), and a bonding sheet (BS) (Mitarai paragraph 60: the insulating film may comprise an Ajinomoto build-up film (ABF)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating bodies of Kanda from an Ajinomoto build-up film (ABF) as taught by Mitarai because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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/JOHN B FREAL/Examiner, Art Unit 2847