DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13 - 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 13, 2026.
Specification
The disclosure is objected to because of the following informality: The acronym “SR” does not appear to be defined in the disclosure.
Appropriate correction is required.
Claim Objections
Claims 1, 2, and 12 are objected to because of the following informalities:
Regarding claim 1, on line 7, the acronym “SR” is not defined. Please define “SR” layer as solder resist layer (i.e., solder resist (“SR”) layer). Only one occurrence is necessary;
Regarding claim 2, line 1 contains a typographical error (“method of c circuit board” should be “method of a circuit board”;
Regarding claim 12, on line 1, “prior to the step of (h)” should be “prior to the step (h),” (please include the comma after (h)); and
Regarding claim 12, a period (“.”) is needed at the end of the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the substrate" on line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu et al. (Japanese Patent Publication No. 2016-035987A).
Regarding claim 1, in Figures 9 – 16, Shimizu discloses a manufacturing method of a circuit board, comprising steps of: (a) fabricating a cavity (30, Figures 5 and 9(B)) with a predetermined depth in the board; (b) applying an adhesive (36, 33, Figures 2 and 10(A)) on the bottom surface of the cavity; (c) installing a bridge element (80, Figure 10(A)) on the adhesive and adjusting the height level in such a way that the top surface of the installed bridge element is aligned to that of the outer layer of the substrate (Figure 10(A)); (d) forming an SR layer (29, Figure 13) by pasting a solder resist all over the bridge element and the outer layer of the substrate; (e) making SR openings (27, 27A, Figure 13) in the SR layer on the outer layer of the substrate; (f) making SR openings (27B, Figure 14) in the SR layer on the bridge element; (g) forming copper pillars (23/25, 23A/25A, 23B/25B, Figures 13 and 14) in the SR openings by electroplating; and (h) mounting chips in such a way that the electrodes of the chips are in contact with the copper pillars (electrodes of external chips make contact with pads 23, 23A, 23B, Figure 16; claim 9 – “connecting the electronic component with the electronic component”).
Regarding claim 2, in Figures 9 – 16, Shimizu discloses a manufacturing method of a circuit board, comprising steps of: (a) fabricating a cavity (30, Figures 5 and 9(B)) with a predetermined depth in the substrate; (b) applying an adhesive (36, 33, Figures 2 and 10(A)) on the bottom surface of the cavity; (c) installing a bridge element (80, Figure 10(A)) on the adhesive and adjusting the height level in such a way that the top surface of the installed bridge element is aligned to that of the outer layer of the substrate (Figure 10(A)); (d) forming an SR layer (29, Figure 13) by pasting a solder resist all over the bridge element and the outer layer of the substrate; (e) making SR openings (27, 27A, Figure 13) in the SR layer on the outer layer of the substrate; (f) making SR openings (27B, Figure 14) in the SR layer on the bridge element; (g) forming copper pillars (23, 23A, 23B, Figures 13 and 14) in the SR openings on the bridge element and partly in the SR openings on the outer layer of the substrate by electroplating; (h) forming microballs (25, 25A, Figures 13 and 14) partly in the SR openings on the outer layer of the substrate; and (i) mounting chips in such a way that the electrodes of the chips are in contact with the copper pillars (electrodes of external chips make contact with pads 23, 23A, 23B, Figure 16; claim 9 – “connecting the electronic component with the electronic component”).
Regarding claim 3, Shimizu discloses that the adhesive of the step (b) is DAF(Dry Adhesive Film) (Figures 9 – 16).
Regarding claim 4, Shimizu discloses that said bridge element comprises the electrode on top surface for electrical connection to chips and a wiring layer in the resin-based substrate (Figures 9 – 16).
Regarding claim 5, Shimizu discloses said SR openings of the step (f) are made either by laser drill or by photolithography comprising mask printing, photo- exposure for pattern transfer, develop, and etch processes (Figures 9 – 16).
Regarding claim 6, Shimizu discloses that said SR openings of the step (e) are made by photolithography comprising mask printing, photo-exposure for pattern transfer, develop, and etch processes (Figures 9 – 16).
Regarding claim 7, Shimizu discloses that said copper pillars are bumps which are formed by Cu/Ni/Sn electroplating (Figures 9 – 16).
Regarding claim 8, Shimizu discloses that the adhesive of the step (b) is DAF(Dry Adhesive Film) (Figures 9 – 16).
Regarding claim 9, Shimizu discloses that said bridge element comprises the electrode on top surface for electrical connection to chips and a wiring layer in the resin-based substrate (Figures 9 – 16).
Regarding claim 10, Shimizu discloses that said SR openings of the step (f) are made either by laser drill or by photolithography comprising mask printing, Page 10 of 13 photo-exposure for pattern transfer, develop, and etch processes (Figures 9 – 16).
Regarding claim 11, Shimizu discloses that said SR openings of the step (e) are made by photolithography comprising mask printing, photo-exposure for pattern transfer, develop, and etch processes (Figures 9 – 16).
Regarding claim 12, Shimizu discloses that prior to the step of (h) gold(Au) electroplating for finish-treatment is performed in the SR openings on the outer layer of the substrate (Figures 9 – 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847