DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the first set of one or more metal structures extending through the first dielectric layer " in line 1 and 2. There is insufficient antecedent basis for this limitation in the claim. Examiner is under the impression that applicant meant to state “ first set of one or more metal connectors that extends through the first dielectric layer” from claim 1. Examiner will examine under this assumption.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-16, 18-24, and 26-30 are rejected under 35 U.S.C. 102(a)(1) based upon a public use or sale or other public availability of the invention, and are anticipated by Kuiwon Kang et al. (US 20200388573 A1) Hereinafter referred to as “Kang”.
Regarding claim 1 Kang teaches
An electronic device (Fig 9 Para [0018]), comprising:
a substrate (200 or 600, Para [0015]), the substrate comprising:
at least two stacked embedded trace substrates (ETS) (Fig 6D element 610 and 650 Para [0040] [0015]);
a first dielectric layer (632 Para [0103]) disposed between an internally facing surface (bottom edge of 610 Fig 6A) of a first ETS (610) of the at least two stacked ETS with an internally facing surface (top edge of 650 Fig 6B) of a second ETS(650) of the at least two stacked ETS; and
a first set of one or more metal connectors(630 and 634) that extends through the first dielectric layer (632) and couples a first set of one or more metal structures at the internally facing surface of the first ETS (620 and the material, that goes deeper into 610, that it is attached to in Fig 6A) with a second set of one or more metal structures at the internally facing surface of the second ETS. (620 and the material, that goes deeper into 650, that it is attached to in Fig 6B)
Regarding claim 2 Kang teaches
The electronic device of claim 1, wherein:
the first set of one or more metal structures at the internally facing surface of the first ETS comprises one or more raised pads (the portion of 620 in 610 of fig 6a that is protruding out from the insulating layers.); and
the second set of one or more metal structures at the internally facing surface of the second ETS comprises one or more embedded pads (the portion of 620 in 650 of fig 6b that sits recessed and further deep in the insulating layers ).
Regarding claim 3 Kang teaches
The electronic device of claim 2, wherein the first set of one or more metal structures (630 and 634) extending through the first dielectric layer comprises:
at least one metallized bump (634 Para [0101][0027]) disposed between at least one of the one or more embedded pads of the second ETS and at least one of the one or more raised pads of the first ETS. (fig 2 or fig 6A-6D)
Regarding claim 4 Kang teaches
The electronic device of claim 3, wherein:
the at least one metallized bump (fig 6A-D element 634 Para [0027][0101] )is formed from a metal different (Para [0030][0097]) than a metal used to form the one or more embedded pads and the one or more raised pads.
Regarding claim 5 Kang teaches
The electronic device of claim 1, wherein:
the first ETS (610) includes a first outer surface (top edge of 610 of Fig 6A or 210 of Fig 2) including one or more embedded pads (220) disposed in a second dielectric layer (216 or 616 Para [0044]) where the plurality of layers may look like a layer between each metallization layers giving the invention three layers, like the sister embodiment shown and labeled in figure 5e, or some other configuration).
Regarding claim 6 Kang teaches
The electronic device of claim 5, further comprising:
an integrated circuit (IC) component (404b of Fig 4) disposed on the first outer surface of the first ETS (the top surface of 610 corresponds to the top edge of 400 Para [0078][0104]) and electrically connected to the one or more embedded pads of the first ETS. (Para [0104])
Regarding claim 7 Kang teaches
The electronic device of claim 6, wherein:
the IC component is disposed on the first outer surface of the first ETS (Para [0104]) without a solder mask layer (Kang makes no mention of a solder mask layer) at the first outer surface of the first ETS.
Regarding claim 8 Kang teaches
The electronic device of claim 1, wherein:
the second ETS (650) includes a second outer surface (lower edge of 650 fig 6B) including one or more exposed embedded pads disposed in a third dielectric layer. (256 or 656 Para [0099] where the plurality of layers may look like a layer between each metallization layers giving the invention three layers, like the sister embodiment shown and labeled in figure 5e, or some other configuration).
Regarding claim 9 Kang teaches
The electronic device of claim 8, further comprising:
one or more solder joints (Para [0038][0027] Fig 1) connecting the one or more exposed embedded pads (Para [0038]) to one or more metal terminals (Para[0081]) of a printed circuit board. (116 Para [0041][0027][0038][0037][0081])
Regarding claim 10 Kang teaches
The electronic device of claim 9, wherein:
the second outer surface of the second ETS (bottom of 650) is disposed on the printed circuit board (116 Para [0041][0027][0038][0037][0081]) without an intermediate solder mask layer (Kang make no mention of a solder mask) formed on the second outer surface of the second ETS.
Regarding claim 11 Kang teaches
The electronic device of claim 1, wherein:
the first ETS and the second ETS are each multilayer ETS structures. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Regarding claim 12 Kang teaches
The electronic device of claim 11, wherein:
the first ETS is a three-layer ETS structure;
the second ETS is a three-layer ETS structure; or
a combination thereof. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Regarding claim 13 Kang teaches
The electronic device of claim 1, wherein the electronic device comprises at least one of:
a music player; a video player; an entertainment unit; a navigation device; a communications device; a mobile device; a mobile phone; a smartphone (Para[0118] Fig 9);
a personal digital assistant; a fixed location terminal; a tablet computer, a computer; a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle.
Regarding claim 14 Kang teaches
A substrate (200 or 600, Para [0015]) comprising:
at least two stacked embedded trace substrates (ETS) overlying one another (Fig 6D element 610 and 650 Para[0040] [0015]);
a first dielectric layer (632 Para[0103]) joining an internally facing surface (bottom edge of 610 Fig 6A) of a first ETS (610) of the at least two stacked ETS with an internally facing surface (top edge of 650 Fig 6B) of a second ETS (650) of the at least two stacked ETS; and
a first set of one or more metal structures extending through the first dielectric layer (630 and 634 extend through 632) and connecting a first set of one or more metal structures at the internally facing surface of the first ETS (620 and the material, that goes deeper into 610, that it is attached to in Fig 6A) with a second set of one or more metal structures at the internally facing surface of the second ETS. (620 and the material, that goes deeper into 650, that it is attached to in Fig 6B)
Regarding claim 15 Kang teaches
The substrate of claim 14, wherein:
the first set of one or more metal structures at the internally facing surface of the first ETS comprises one or more raised pads (the portion of 620 in 610 of fig 6a that is protruding out from the insulating layers); and
the second set of one or more metal structures at the internally facing surface of the second ETS comprises one or more embedded pads. (the portion of 620 in 650 of fig 6b that sits recessed and further deep in the insulating layers )
Regarding claim 16 Kang teaches
The substrate of claim 15, wherein the first set of one or more metal structures (Fig 6A-D elements 630 and 634) extending through the first dielectric layer comprises:
at least one metallized bump (634) disposed between at least one of the one or more embedded pads of the second ETS and at least one of the one or more raised pads of the first ETS. (Fig 2 or fig 6A-6D)
Regarding claim 17 Kang teaches
The substrate of claim 16, wherein:
the at least one metallized bump(fig 6A-D element 634 Para [0027][0101] ) is formed from a metal different (Para [0030][0097]) than a metal used to form the one or more embedded pads and the one or more raised pads.
Regarding claim 18 Kang teaches
The substrate of claim 14, wherein:
the first ETS (610) includes a first outer surface (top edge of 610 of Fig 6A) including one or more embedded pads (620) disposed in a second dielectric layer. (616 Para [0044])
Regarding claim 19 Kang teaches
The substrate of claim 14, wherein:
the second ETS (650) includes a second outer surface ((lower edge of 650 fig 6B) including one or more exposed embedded pads disposed in a third dielectric layer. (656 Para [0099])
Regarding claim 20 Kang teaches
The substrate of claim 14, wherein:
the first ETS and the second ETS are each multilayer ETS structures. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Regarding claim 21 Kang teaches
The substrate of claim 20, wherein:
the first ETS is a three-layer ETS structure;
the second ETS is a three-layer ETS structure; or
a combination thereof. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Regarding claim 22 Kang teaches
A method of fabricating a substrate, comprising:
aligning at least two stacked embedded trace substrates (ETS) (Fig 6D element 610 and 650 Para[0040] [0015]) to overlie one another, wherein the at least two stacked ETS include a first ETS (610) having an internally facing surface (bottom edge of 610 Fig 6A) having a first set of one or more metal connectors (620 and the material, that goes deeper into 610, that it is attached to in Fig 6A), and a second ETS(650) having an internally facing surface (top edge of 650 Fig 6B) having a first set of one or more metal structures (620 and the material, that goes deeper into 650, that it is attached to in Fig 6B);
aligning a first dielectric layer (632 Para[0103]) between the internally facing surface of the first ETS and the internally facing surface of the second ETS; and
joining the internally facing surface of the first ETS and the internally facing surface of the second ETS with the first dielectric layer, wherein the joining connects at least one metal structure of the first set of one or more metal connectors (620 of 610) at the internally facing surface of the first ETS with at least one metal structure of the first set of one or more metal structures at the internally facing surface of the second ETS. (620 of both 610 and 650 are joined)
Regarding claim 23 Kang teaches
The method of claim 22, wherein:
the first set of one or more metal connectors at the internally facing surface of the first ETS includes one or more raised pads (the portion of 620 in 610 of fig 6a that is protruding out from the insulating layers.); and
the first set of one or more metal structures at the internally facing surface of the second ETS include one or more embedded pads. (the portion of 620 in 650 of fig 6b that sits recessed and further deep in the insulating layers )
Regarding claim 24 Kang teaches
The method of claim 23, further comprising:
forming at least one metallized bump (fig 6A-D element 634 Para [0027][0101] )disposed between at least one embedded pad of the second ETS and at least one raised pad of the first ETS. (fig 2 or fig 6A-6D)
Regarding claim 25 Kang teaches
The method of claim 24, wherein:
the at least one metallized bump (fig 6A-D element 634 Para [0027][0101] ) is formed from a metal different (Para [0030][0097]) than a metal used to form the at least one embedded pad of the second ETS and the at least one raised pad of the first ETS.
Regarding claim 26 Kang teaches
The method of claim 22, wherein:
the first ETS (610)includes a first outer surface (top edge of 610 of Fig 6A) having one or more embedded pads (620)disposed in a second dielectric layer. (616 Para [0044])
Regarding claim 27 Kang teaches
The method of claim 22, wherein:
the second ETS (650) includes a second outer surface (lower edge of 650 fig 6B) having one or more exposed embedded pads disposed in a third dielectric layer. (656 Para [0099] where the plurality of layers may look like a layer between each metallization layers giving the invention three layers, like the sister embodiment shown and labeled in figure 5e, or some other configuration).
Regarding claim 28 Kang teaches
The method of claim 22, wherein:
the first ETS and the second ETS are each multilayer ETS structures. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Regarding claim 29 Kang teaches
The method of claim 22, further comprising: forming the first ETS(Fig 6A-D 610); and forming the second ETS. (650) (they exist therefore they were formed)
Regarding claim 30 Kang teaches
The method of claim 29, wherein:
the first ETS is formed as a three-layer ETS structure;
the second ETS is formed as a three-layer ETS structure; or
the first ETS and second ETS are each formed as three-layer structures. (250 and 210 and thusly 610 and 650 each could have a three-layer ETS structure defined by the three dielectric layers Para [0044][0099])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. ZHAO; Allen et al. (US-20230128938-A1), KANG; Kuiwon et al. (US-20210407918-A1), FURUTANI, TOSHIKI et al. (CN-116095949-A), KANG KUIWON et al. (KR-20230053604-A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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