DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election with traverse of Invention I, identified as encompassing claims 1-16 is acknowledged.
The arguments present the opinion that examination of both inventions would be more efficient and minimal additional search such that there would be serious additional burden. The arguments discuss the similarities and lack of mutually exclusive characteristics. The Examiner notes that the restriction is between a method and a device requiring a showing of independent and/or distinctness, not a restriction between species, as detailed in the restriction requirement. It is further noted that the restriction is not merely based on the initial claim set and rather the grouped inventions in their entirety.
Therefore, the restriction is maintained and made final.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 1 is rejected under 35 U.S.C. 103 as obvious over Wiatr et al. (US 2009/0111223 A1), hereinafter as W1, in view of Sharma et al. (US 2018/0374931 A1), hereinafter as S1
5. Regarding Claim 1, W1 discloses a method for fabricating a device (see in particular Figs. 2a-g), comprising:
providing a semiconductor layer-stack (elements 202, 204-207 and [0031] “semiconductor layer 205”) having one or more layers and a substrate layer (element 201,202 see [0031] “substrate 201”);
implanting a first dopant (see Fig. 2c dopants into the region of element 211, see [0034] “an N-well region 211 is to be formed, while, in other cases, a P-type dopant may be introduced when a P-well is required for the substrate diode still to be formed. For instance, arsenic ions or phosphorous ions may be used on the basis of well-established implantation recipes”) using a first mask (element 231, see [0034] “implantation mask 231”) to form a first region (region of element 211) spanning a first lateral portion of the substrate layer (see Fig. 2c);
etching a via (see Fig. 2e-f opening of element 214A and see [0039] “forming the openings 214A, 214B on the basis of the etch process 233”) through the one or more layers and into a top portion of the substrate layer (see Fig. 2f);
implanting a second dopant (see [0038] “the transistor 223A may represent an N-channel transistor … the highly doped region 215A may have substantially the same dopant concentration as the drain and source regions 224A” and [0037] “diode PN junction still to be formed in the well junction 211”) using a second mask (element 235 in the process of forming element 215A, see [0038]) to form one or more second regions (element 215A) spanning one or more second lateral portions (portion of element 215A) of the substrate layer, wherein the one or more second lateral portions resides within the first lateral portion (see Fig. 2f); and
implanting the first dopant using a third mask (element 235 used during forming of element 215B, see [0038]) to form one or more third regions (see [0038] “doped region 215B” and Fig. 2g n+ doping) spanning one or more third lateral portions of the substrate layer (see Fig. 2g), wherein the one or more third lateral portions resides within the first lateral portion (see Fig. 2g).
W1 does not explicitly disclose the substrate is high resistivity.
S1 discloses the substrate is high resistivity (see [0116] “semiconductor material 302 may be a high resistivity substrate”).
The resistivity of the semiconductor substrate as taught by S1 is incorporated as the resistivity of the semiconductor substrate of W1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with W1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known resistivity of a semiconductor material substrate for another for which the resistivity is provided as selectable to obtain predictable results (see S1 [0116]).
6. Claim 5 is rejected under 35 U.S.C. 103 as obvious over Wiatr et al. (US 2009/0111223 A1), hereinafter as W1, in view of Sharma et al. (US 2018/0374931 A1), hereinafter as S1, in view of Lu (US 2021/0407859 A1), hereinafter as L1
7. Regarding Claim 5, W1, S1 disclose the method of claim 1, wherein etching the via further comprises etching one or more vias to form vias at each of the one or more second regions and each of the one or more third regions (see W1 Fig. 2g and [0042] “sophisticated lithography processes and anisotropic etch steps for forming openings connecting to the transistors 223A, 223B and the substrate diode 215. Thereafter, an appropriate conductive material may be filled into the openings, thereby forming the contacts 216, 226”).
W1, S1 do not disclose using a fourth mask to form vias at a center
L1 discloses using a fourth mask to form vias at a center (see Fig. 24 (a)-(b) and [0152] “the contact-hole opening is located at the center of both the boundary of the source region and the drain region … using photolithographic masking process step and further using complex etching process technique”).
The mask and center via as taught by L1 is incorporated as a mask and center via of W1, S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with W1 because the combination allows for small dimension contact hole with self-alignment (see L1 [0152]); further, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known via location with respect to the underlying doped region for another to obtain predictable results (see L1 Fig. 24 and [0152]).
8. Claim 7 is rejected under 35 U.S.C. 103 as obvious over Wiatr et al. (US 2009/0111223 A1), hereinafter as W1, in view of Sharma et al. (US 2018/0374931 A1), hereinafter as S1, in view of Peters Dethard (DE 102007033810 A1, see attached translation document), hereinafter as P1
9. Regarding Claim 7, W1, S1 disclose the method of claim 1, further comprising:
depositing a metal in the etched via, thereby forming a contact between the deposited metal and a surface of the top portion of the high resistivity substrate layer (see Fig. 2g elements 216 and see [0041] “metallization structure”).
W1, S1 do not explicitly disclose the contact is a Schottky contact.
P1 discloses the contact is a Schottky contact (see Fig. 1 and pg. 6 “anode contact 15 with the negative pole of a voltage source and the cathode contact 14 are connected to the positive pole of a voltage source flows in comparison to the pn diode T .sub.0 of 1 due to the metal-semiconductor junction formed in the overlapping region (Schottky contact)”)
The type of contact as taught by P1 is incorporated as the type of contact for W1, S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with W1,S1 because the combination allows for mitigating of leakage current and insufficient overvoltage resistance (see P1 pg. ); furthermore the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known resistivity of a semiconductor material substrate for another for which the resistivity is provided as selectable to obtain predictable results (see S1 [0116]).
10. Claim 8 is rejected under 35 U.S.C. 103 as obvious over Wiatr et al. (US 2009/0111223 A1), hereinafter as W1, in view of Sharma et al. (US 2018/0374931 A1), hereinafter as S1, in view of Hebert (US 2002/0117714 A1), hereinafter as H1
11. Regarding Claim 8, W1, S1 disclose the method of claim 1.
W1, S1 do not disclose wherein the first dopant is doped at an implantation energy ranging between 100 keV and 800 keV (e.g., high implantation energy).
H1 discloses wherein the first dopant is doped at an implantation energy ranging between 100 keV and 800 keV (e.g., high implantation energy) (see [0036] “highly doped N-type N-well contact region … implanted at a dose in the range of 1x1015 to 1x1016 dopants/cm2 at an energy level in the range of 50 to 180 KeV”; See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The implantation energy range for the first dopant as taught by H1 is incorporated as implantation energy range for the first dopant of W1, S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with W1,S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known implantation energy range for another in a similar highly doped N-well region to obtain predictable results (see H1 [0036])
12. Claims 9-10 are rejected under 35 U.S.C. 103 as obvious over Wiatr et al. (US 2009/0111223 A1), hereinafter as W1, in view of Sharma et al. (US 2018/0374931 A1), hereinafter as S1, in view of Egawa et al. (US 2004/0173866 A1), hereinafter as E1
13. Regarding Claim 9, W1, S1 disclose the method of claim 1.
W1, S1 do not explicitly disclose wherein the second dopant is doped with an implantation dosage between 10¹² and 5x10¹³ (e.g., high dosage) and at an implantation energy ranging between 10 keV and 100 keV (e.g., low implantation energy).
E1 discloses wherein the second dopant is doped with an implantation dosage between 10¹² and 5x10¹³ (e.g., high dosage) and at an implantation energy ranging between 10 keV and 100 keV (e.g., low implantation energy) (see [0058] “implanting boron as p-type impurities are as follows: tilt angle=45°, energy=100 keV and amount of dose=1013 cm-2.”)
The dopant dosage and implantation energy as taught by E1 is incorporated as the dopant dosage and implantation energy of W1, S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of E1 with W1,S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known implantation energy range for another in a similar P-well region to obtain predictable results (see E1 [0058]).
14. Regarding Claim 10, W1, S1 disclose the method of claim 1, wherein (see W1):
the first dopant is p-type (see [0034] “In the embodiment shown, an N-well region 211 is to be formed, while, in other cases, a P-type dopant may be introduced when a P-well is required for the substrate diode still to be formed”), and the second dopant is phosphorous or arsenic (see [0034] “arsenic ions or phosphorous ions may be used”); or
the first dopant is phosphorous or arsenic (see [0034] “arsenic ions or phosphorous ions may be used”), and the second dopant is p-type (see [0034] “In the embodiment shown, an N-well region 211 is to be formed, while, in other cases, a P-type dopant may be introduced when a P-well is required for the substrate diode still to be formed”).
W1, S1 do not explicitly disclose the p-type dopant is boron.
The first p-type dopant is boron or the second p-type dopant is boron
E1 discloses the p-type dopant is boron (see [0058] “implanting boron as p-type impurities”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of E1 with W1,S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific p-type dopant for another in a similar P-well region to obtain predictable results (see E1 [0058]).
Allowable Subject Matter
15. Claims 11-15 are allowed
Claims 2-4 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
16. Claim 2, “the one or more second regions comprise three second regions, wherein a middle second region of the three second regions is smaller in lateral dimensions than two outer second regions of the three second regions, and wherein the middle second region is equal distant from the two outer second regions” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on claim 2 incorporate the same allowable subject matter.
17. Claim 4, “the one or more layers comprise a thin silicon layer and a buried oxide layer, and wherein etching the via comprises etching the via through the thin silicon layer and the buried oxide layer, and into the top portion of the high resistivity substrate layer” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 6, “etching the via further comprises etching one or more vias using a fourth mask to form vias at a center of the two outer second regions without forming a via at a center of the middle second region” – as instantly claimed and in combination with the additionally claimed limitations.
19. Claim 11, “etching one or more vias through the top silicon layer, the buried oxide layer, and a top portion of the high resistivity substrate layer; implanting a second dopant using a second mask to form one or more positive regions spanning one or more second lateral portions of the high resistivity substrate layer, wherein the one or more second lateral portions resides within the first lateral portion; implanting the first dopant using a third mask to form one or more third regions spanning one or more third lateral portions of the high resistivity substrate layer, wherein the one or more third lateral portions resides within the first lateral portion; and depositing a metal in the one or more etched vias to form one or more metal contacts, wherein the one or more metal contacts are formed at centers of the one or more positive regions, thereby forming a bipolar junction transistor” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on claim 11 incorporate the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; pertinent prior art(s) and most relevant portion(s) is provided:
US 20200388696 (Figs. 1-10)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL PARK/Examiner, Art Unit 2818
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