DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al., hereinafter Val (US 2022/0077062 A1) in view of West et al. (US 2017/0098623 A1).
Regarding independent claim 1: Van teaches (e.g., Figs. 7A-7B and 8A-8B; and annotated Figure 8A; [0010]) a semiconductor structure comprising:
a first source/drain (S/D) region ([0048]: 124a) of a first transistor ([0046] and [0048]: 120a) and
a second S/D region (S/D) region (Fig. 8B;[0036] and [0048]: 124b) of a second transistor ([0046]: 102b);
a first backside contact (BC) (Annotated Fig. 8A) conductively connected to the first S/D region (Annotated Fig. 8A),
the first BC having a first longitudinal axis (Annotated Fig. 8A; and
a second BC (Annotated Fig. 8A) conductively connected to the second S/D region,
the second BC having a second longitudinal axis (Annotated Fig. 8A),
wherein the first longitudinal axis of the first BC (Annotated Fig. 8A) intersects with the second longitudinal axis of the second BC in an acute angle (Annotated Fig. 8A).
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Van does not expressly teach a metal contact.
West teaches (e.g., Figs. 1 and 3) a semiconductor structure comprising a backside metal contact ([0018]: 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Van, the metal backside contact, as taught by West for the benefits, of increasing the signal speed of the device by reducing the contact resistance to the source drain regions, and thus, improving device functionality.
Regarding claim 6: Van and West teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends, further comprising
a third S/D region (Van: Annotated Fig. 8A) of a third transistor (Van: Annotated Fig. 8A) next to the first S/D region of the first transistor (Van: Annotated Fig. 8A),
the third S/D region being on top of a placeholder (Van: Annotated Fig. 8A), the placeholder being materially different from the first backside S/D contact (Van: Annotated Fig. 8A).
Regarding independent claim 16: Van teaches (e.g., Figs. 7A-7B and 8A-8B; and annotated Figure 8A; [0010]) a semiconductor structure comprising:
a first source/drain (S/D) region (Annotated Fig. 8A) of a first transistor (Annotated Fig. 8A) on top of a first backside S/D contact (Annotated Fig. 8A);
a second S/D region (Annotated Fig. 8A) of a second transistor (Annotated Fig. 8A) on top of a second backside S/D contact (Annotated Fig. 8A);
a first backside contact (BC) (Annotated Fig. 8A) conductively connected to the first S/D region (Annotated Fig. 8A) through the first backside S/D contact (Annotated Fig. 8A),
the first BC having a first longitudinal axis (Annotated Fig. 8A); and
a second BC (Annotated Fig. 8A) conductively connected to the second S/D region (Annotated Fig. 8A) through the second backside S/D contact (Annotated Fig. 8A),
the second BC having a second longitudinal axis (Annotated Fig. 8A),
wherein the first longitudinal axis of the first BC (Annotated Fig. 8A) intersects with the second longitudinal axis of the second BC (Annotated Fig. 8A) in an angle between 10 and 90 degrees (Annotated Fig. 8A).
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Van does not expressly teach a metal contact.
West teaches (e.g., Figs. 1 and 3) a semiconductor structure comprising a backside metal contact ([0018]: 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Van, the metal backside contact, as taught by West for the benefits, of increasing the signal speed of the device and thus improving device functionality.
Regarding claim 20: Van and West teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
further comprising a third S/D region (Van: Annotated Fig. 8A; 114a) of a third transistor (Van: Annotated Fig. 8A; 114a) next to the first S/D region of the first transistor (Van: Annotated Fig. 8A; 114a) and a frontside S/D contact contacting the third S/D region of the third transistor,
the third S/D region being on top of a placeholder (Van: Annotated Fig. 8A; 114a), the placeholder being materially different from the first backside S/D contact (Van: Annotated Fig. 8A; 114a).
Claims 2-5 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al., hereinafter Val (US 2022/0077062 A1) in view of West et al. (US 2017/0098623 A1) as applied above and further in view of Kim et al. (US 2021/0375722 A1).
Regarding claim 2: Van and West teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends,
Van as modified by West teaches that the first BCM is conductively connected to the first S/D region (Van: Annotated Fig. 8A) via a first backside S/D contact (Van: Annotated Fig. 8A).
Van as modified by West does not teaches that the first backside S/D contact having a liner at sidewalls thereof and having a horizontal width that is substantially same as a bottom width of the first S/D region.
Kim teaches (e.g., Figs. 2-3) a semiconductor structure comprising a first backside S/D contact ([0034]: left side 120) having a liner ([0034]: 131) at sidewalls thereof and having a horizontal width that is substantially same as a bottom width of a first S/D region (Fig. 2; [0041]: 110 of fin 105 on the left side; substantially same is a term of degree and subject to interpretation; thus, the requirement of the claimed invention is met because horizontal width of first backside S/D contact is substantially same as the source/drain region of a left side FinFET).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Van as modified by West, the first backside S/D contact having a liner at sidewalls thereof and having a horizontal width that is substantially same as a bottom width of the first S/D region, as taught by Kim, for the benefits of protecting the surrounding device regions from metal diffusion and thus improving device liability.
Regarding claim 3: Van, West and Kim teach the claim limitation of the semiconductor structure of claim 2, on which this claim depends,
Van as modified by West and Kim teaches that the first BCM has a first width measured in a direction perpendicular to the first longitudinal axis (Van: Annotated Fig. 8A),
the first width being equal to or larger than the horizontal width of the first backside S/D contact (Van: Annotated Fig. 8A; 114a).
Regarding claim 4: Van, West and Kim teach the claim limitation of the semiconductor structure of claim 2, on which this claim depends,
Van as modified by West and Kim teaches that
the first and the second BCM (Kim: 120 left side and 120 right side respectively) are embedded in a dielectric layer (Kim: [0041]: 165),
the first longitudinal axis of the first BCM (Van: Annotated Fig. 8A) forming a first angle with a normal of the dielectric layer between 5 and 45 degrees (Kim: 165), and
the second longitudinal axis of the second BCM (Van: Annotated Fig. 8A) forming a second angle with the normal of the dielectric layer between -5 and -45 degrees (Kim: 165).
Regarding claim 5: Van, West and Kim teach the claim limitation of the semiconductor structure of claim 2, on which this claim depends,
Van as modified by West and Kim teaches that
the first BCM (Kim: left side 120) is in contact with a first backside power rail (BPR) (Kim: [0053]: left side ML2) and
the second BCM (Kim: right side 120) is in contact with a second BPR (Kim: [0053]: right side ML2),
a distance between the first and the second BPR (Kim: [0053]: left side and right side ML2) is larger than a distance between the first and the second S/D region (Kim: [0026]: left side and right side S/D regions 110).
Regarding claim 8: Van and West teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Van as modified by West does not expressly teach that
the first S/D region comprises phosphorus-doped epitaxial silicon, and
the second S/D region comprises boron-doped epitaxial silicon-germanium.
However, Van teaches the second S/D region comprises epitaxial silicon-germanium (Van: [0058]: 124b comprise doped silicon germanium or some other suitable doped semiconductor material”).
Kim teaches (e.g., Figs. 2-3) a semiconductor structure comprising
a first S/D region comprises phosphorus-doped epitaxial silicon ([0026]), and
a second S/D region comprises boron-doped epitaxial silicon-germanium ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Van as modified by West, the first S/D region comprising phosphorus-doped epitaxial silicon, and the second S/D region comprising boron-doped epitaxial silicon-germanium, as taught by Kim, for the benefits of improving the electrical carrier density and mobility; thus, improving the transistor functionality.
Regarding claim 17: Van and West teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
wherein the first backside S/D contact includes a liner at sidewalls thereof and has a horizontal width that is substantially same as a bottom width of the first S/D region.
Van as modified by West does not teaches that the first backside S/D contact includes a liner at sidewalls thereof and has a horizontal width that is substantially same as a bottom width of the first S/D region.
Kim teaches (e.g., Figs. 2-3) a semiconductor structure comprising a first backside S/D contact ([0034]: left side 120) having a liner ([0034]: 131) at sidewalls thereof and having a horizontal width that is substantially same as a bottom width of a first S/D region (Fig. 2; [0041]: 110 of fin 105 on the left side; substantially same is a term of degree and subject to interpretation; thus, the requirement of the claimed invention is met because horizontal width of first backside S/D contact is substantially same as the source/drain region of a left side FinFET).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Van as modified by West, the first backside S/D contact includes a liner at sidewalls thereof and has a horizontal width that is substantially same as a bottom width of the first S/D region, as taught by Kim, for the benefits of protecting the surrounding device regions from metal diffusion and thus improving device liability.
Regarding claim 18: Van and West teach the claim limitation of the semiconductor structure of claim 17, on which this claim depends,
Van as modified by West and Kim teaches that the first BCM have a first width in a direction perpendicular to the first longitudinal axis (Van: Annotated Fig. 8A),
the first width being equal to or larger than the horizontal width of the first backside S/D contact (Van: Annotated Fig. 8A; 114a).
Regarding claim 19: Van and West teach the claim limitation of the semiconductor structure of claim 17, on which this claim depends,
Van as modified by West and Kim teaches that
the first BCM (Kim: left side 120) is in contact with a first backside power rail (BPR) (Kim: left side 120) and
the second BCM (Kim: right side 120) is in contact with a second BPR (Kim: [0053]: right side ML2),
a distance between the first and the second BPR (Kim: [0053]: left side and right side ML2) is larger than a distance between the first and the second S/D region (Kim: [0026]: left side and right side S/D regions 110).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al., hereinafter Val (US 2022/0077062 A1) in view of West et al. (US 2017/0098623 A1) as applied above and further in view of Wang et al. (US 2021/0305262 A1).
Regarding claim 7: Van and West teach the claim limitation of the semiconductor structure of claim 6, on which this claim depends.
Van as modified by West does not expressly teach that the device further comprises a frontside S/D contact contacting the third S/D region of the third transistor.
Wang teaches (e.g., Fig. 5A) a semiconductor structure comprising a frontside S/D contact ([0042]: on left side MD) contacting a third S/D region of a third transistor ([0042]: 502b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Van as modified by West, the frontside S/D contact contacting the third S/D region of the third transistor, as taught by Wang, for the benefits, of avoiding crowding the interconnection structure on a small area by spreading the contacts on both top and bottom surfaces and thus improving device interconnection reliability and at the same time, avoiding signal interference.
Claims 9-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al., hereinafter Val (US 2022/0077062 A1) in view of West et al. (US 2017/0098623 A1) and Lee et al. US 20240274676 A1
Regarding independent claim 9: Van teaches (e.g., Figs. 7A-7B and 8A-8B; and annotated Figure 8A; [0010]) a method of forming a semiconductor structure comprising:
forming a first source/drain (S/D) region (Annotated Fig. 8A) on top of a first placeholder (Annotated Fig. 8A) and a second S/D region (Annotated Fig. 8A) on top of a second placeholder (Annotated Fig. 8A);
creating a first angled opening in a dielectric layer underneath the first and the second placeholder,
the first angled opening exposing the first placeholder;
selectively removing the first placeholder to create a first opening extension that exposes a bottom surface of the first S/D region;
filling the first opening extension with a conductive material to form a first backside S/D contact (Annotated Fig. 8A); and
filling the first angled opening with the conductive material to form a first backside contact (BC) (Annotated Fig. 8A) conductively connected to the first S/D region(Annotated Fig. 8A) via the first backside S/D contact (Annotated Fig. 8A).
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Van does not expressly teach
creating a first angled opening in a dielectric layer underneath the first and the second placeholder,
the first angled opening exposing the first placeholder;
selectively removing the first placeholder to create a first opening extension that exposes a bottom surface of the first S/D region;
a metal contact (BC, see [0045], [0135], [0158] and [0161]).
West teaches (e.g., Figs. 1 and 3) a semiconductor structure comprising a backside metal contact ([0018]: 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Van, the metal backside contact, as taught by West for the benefits, of increasing the signal speed of the device and thus improving device functionality.
Lee teaches (e.g., Figs. 10A-10D to Fig. 25) a method comprising
creating a first angled opening (Figs. 10B-24D and Fig. 25, step S50, [0157]-[0158]; initial etching step before fully reaching the source drain structure) in a dielectric layer (Figs. 10B-22E and Fig. 25, step S50, [0157]-[0158]; structure in [0132]-[0133]), [0136] and [0143]: 106) underneath a first and a second placeholder ([0137]-[0138]: P),
the first angled opening (Figs. 10B to 24E and Fig. 25; [0137]-[0138]) exposing the first placeholder (P);
selectively removing the first placeholder (Figs. 22B to 22E and Fig. 25; [0137]-[0138]: P),
to create a first opening extension (Figs. 22B to 22E and Fig. 25; [0137]-[0138]: P) that exposes a bottom surface of a first S/D region (Fig. 25; [0144] and [0146]: SD2; step S60; [0159]-[0156]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Lee, the method of creating a first angled opening in a dielectric layer underneath the first and the second placeholder, the first angled opening exposing the first placeholder; selectively removing the first placeholder to create a first opening extension that exposes a bottom surface of the first S/D region, as taught by Lee, for the benefits, of increasing the area allocated to the interconnection structure and thus improving device integration with other components, thus increasing device functionalities and at the same time avoiding electrical short-circuits.
Regarding claim 10: Van, West and Lee teach the claim limitation of the method of claim 9, on which this claim depends.
Van as modified by West and Lee teaches that the method further comprises
creating a second angled opening (Lee: Figs. 22B-24D and Fig. 25, step S50, [0157]-[0158]; initial etching step before fully reaching the source drain structure) in the dielectric layer to expose the second placeholder (Lee: Figs. 22B-24D and Fig. 25, step S50, [0157]-[0158]; initial etching step before fully reaching the source drain structure; [0137]-[0138]: P);
selectively removing the second placeholder to create a second opening extension (Lee: Figs. 22B to 22E and Fig. 25; [0137]-[0138]: P) that exposes a bottom surface of the second S/D region (Lee: SD, see [0120]);
filling the second opening extension to form a second backside S/D contact (Van: Annotated Fig. 8A); and
filling the second angled opening to form a second BCM (Van: Annotated Fig. 8A) conductively connected to the second S/D region via the second backside S/D contact,
wherein the first BCM has a first longitudinal axis(Van: Annotated Fig. 8A) and the second BCM has a second longitudinal axis (Van: Annotated Fig. 8A), the first and the second longitudinal axis form an acute angle (Van: Annotated Fig. 8A).
Regarding claim 11: Van, West and Lee teach the claim limitation of the method of claim 9, on which this claim depends.
wherein the dielectric layer (Lee: 106) is deposited on top of the first and the second placeholder (Lee: P) after a set of raw placeholders are polished (Lee: Figs. 21B to Fig. 21E; see [0134]-[0135]) to create the first and the second placeholder (Lee: P).
Regarding claim 14: Van, West and Lee teach the claim limitation of the method of claim 9, on which this claim depends.
Van as modified by West and Lee teach further comprising forming a first backside power rail (BPR) (Kim: [0053]: left side and right side ML2) in contact with the first BCM and
a second BPR (Kim: [0053]: right side ML2) in contact with the second BCM.
Allowable Subject Matter
Claims 12-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a method of forming a semiconductor structure comprising:
“wherein creating the first angled opening in the dielectric layer comprises:
forming a hard mask on top of the dielectric layer, the hard mask having a mask opening,
the mask opening having a horizontal positional offset from the first placeholder; and etching the dielectric layer in an anisotropic etch process to create the first angled opening,
the first angled opening being oriented in a direction connecting the mask opening with the first placeholder”.
Claim 13 depends from claim 12, and therefore, is allowable for the same reason as claim 12.
Regarding claim 15: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a method of forming a semiconductor structure comprising:
“further comprising forming a third S/D region of a third transistor on top of a third placeholder and next to the first S/D region, and
forming a fourth S/D region of a fourth transistor on top of a fourth placeholder and next to the second S/D region,
wherein the third S/D region is contacted by a first frontside S/D contact and the fourth S/D region is contacted by a second frontside S/D contact”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812