DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 05/11/2026.
Applicant’s amendments filed 05/11/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1 and 6; and the cancellation of claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0143214 to Lee et al. (hereinafter Lee) in view of Kang et al. (US 2023/0178476, hereinafter Kang) and Li et al. (US 2022/0223498, hereafter Li).
With respect to claims 1-3, Lee discloses a stacked via structure (e.g., interconnect structure 70 including a plurality via plug structures V1-V3, see the annotated Fig. 8 below) (Lee, Fig. 8, ¶0005-¶0006, ¶0020-¶0033) comprising:
a first source metal (e.g., M1, on the right side of WL2) (Lee, Fig. 8, ¶0021, ¶0032) and a first drain metal (e.g., M1, on the left side of WL2) disposed apart from each other in an interlayer insulation film (e.g., an insulation film of the interconnection 70);
a pair of lower vias (e.g., V1) (Lee, Fig. 8, ¶0026, ¶0032), wherein one of the pair of lower vias (V1) is connected to the first source metal (e.g., M1, on the right side of WL2) and another of the pair of lower vias is connected to the first drain metal (e.g., M1, on the left side of WL2) within the interlayer insulation film (e.g., the insulation film of the interconnection 70);
a pair of upper vias (e.g., V2) (Lee, Fig. 8, ¶0027, ¶0032), wherein one (e.g., V2, on the right side of WL2) of the pair of upper vias is connected (e.g., through the metal M2) to an upper part of the one of the pair of lower vias (V1) and another (e.g., V2, on the left side of WL2) of the pair of upper vias is connected (e.g., through the metal M2) to an upper part of another of the pair of lower vias within the interlayer insulation film;
a second source metal (e.g., M4, on the right side of WL2) (Lee, Fig. 8, ¶0032) connected to the one of the pair of upper vias (V2) and a second drain metal (e.g., M4, on the left side of WL2) connected to another of the pair of upper vias (V2), wherein the second source metal (e.g., M4, on the right side of WL2) and the second drain metal (e.g., M4, on the left side of WL2) are disposed apart from each other.
Further, Lee does not specifically disclose (1) a sidewall disposed at an end of each of the pair of lower vias or at an end of each of the pair of upper vias to surround the end (as claimed in claim 1); wherein the sidewall has a conductive metal material (as claimed in claim 2); wherein the sidewall surrounds an upper outer surface of each of the pair of lower vias (as claimed in claim 3); (2) wherein the sidewall has a flat bottom surface and a curved upper surface (as claimed in claim 1).
Regarding (1), Kang teaches forming an integrated circuit (see the annotated Fig. 3 below) (Kang, Fig. 3, ¶0003, ¶0019-¶0024, ¶0031-¶0040, ¶0048-¶0050, ¶0052-¶0055, ¶0062-¶0064, ¶0071-¶0075) comprising a logic cell including field effect transistors and contact structures, wherein a ring-shaped conductive pattern (274) (Kang, Fig. 3, ¶0048, ¶0074-¶0075) including a sidewall is disposed at an end of each of the pair of lower vias (276) to surround the end, wherein the sidewall has a conductive metal material (e.g., titanium (Ti)) (Kang, Fig. 3, ¶0048); wherein the sidewall surrounds an upper outer surface of each of the pair of lower vias (276), to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the stacked via structure of Lee by forming a ring-shaped conductive pattern including a sidewall surrounding an upper end of the via contact as taught by Kang to have the stacked via structure comprising: a sidewall disposed at an end of each of the pair of lower vias or at an end of each of the pair of upper vias to surround the end (as claimed in claim 1); wherein the sidewall has a conductive metal material (as claimed in claim 2); wherein the sidewall surrounds an upper outer surface of each of the pair of lower vias (as claimed in claim 3), in order to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075, ¶0147).
Regarding (2), Li teaches forming a protective structure (Li, Fig. 5A, ¶0017, ¶0025-¶0032, ¶0037) having a ring shape and including a sidewall (e.g., uppermost ring formed in the dielectric layer 106g) disposed on an outer sidewalls of the via structure (112), wherein the sidewall (Li, Fig. 5A, ¶0032, ¶0037) has a flat bottom surface and a curved upper surface (e.g., stepped surface of the uppermost ring), to protect adjacent dielectric layers, and to provide reliable connection structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the stacked via structure of Lee by forming a ring-shaped conductive pattern including a sidewall having a specific shape and surrounding an upper end of the via contact as taught by Li to have the stacked via structure, wherein the sidewall has a flat bottom surface and a curved upper surface (as claimed in claim 1), in order to protect adjacent dielectric layers, and to provide reliable connection structure (Li, ¶0017, ¶0030-¶0032, ¶0037).
Regarding claim 4, Lee in view of Kang and Li discloses the stacked via structure of claim 2. Further, Lee does not specifically disclose the stacked via, wherein the sidewall is formed by an etching process without a separate mask pattern.
Note that limitations “the sidewall is formed by an etching process without a separate mask pattern” are directed to towards the process of making the sidewall. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the sidewall is formed by an etching process without a separate mask pattern” only requires a structure, the sidewall, which does not distinguish the invention from the combination Lee/Kang that teaches the structure as claimed.
Nevertheless, Kang discloses that the sidewall (e.g., the ring-shaped capping pattern 274) is formed by deposition (Kang, Figs. 8G-8I, ¶0138-¶0147) of the capping layer (154L) including a metal and removing (e.g., by CMP) portions of the capping layer (154L) without a separate mask pattern.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the stacked via structure of Lee/Kang/Li by forming a ring-shaped conductive pattern including a sidewall surrounding an upper end of the via contact as taught by Kang to have the stacked via structure, wherein the sidewall is formed by an etching process without a separate mask pattern, in order to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075, ¶0147).
With respect to claim 6, Lee discloses a semiconductor device (e.g., a memory device including a memory cell region and a logic device region, see the annotated Fig. 8 below) including a stacked via structure (e.g., interconnect structure 70 including a plurality via plug structures V1-V3) (Lee, Figs. 1, 8, ¶0005-¶0006, ¶0020-¶0033), the semiconductor device comprising:
a substrate (10) (Lee, Fig. 8, ¶0021);
a plurality of gate regions (WL1/WL2) (Lee, Figs. 1, 8, ¶0021) disposed on the substrate (10), one (e.g., WL1) of the plurality of gate regions being disposed in a cell region (e.g., memory cell region M) and another (WL2) of the plurality of gate regions being disposed in a peripheral region (e.g., logic device region L);
a source region (e.g., 16, on the right side of WL1) (Lee, Figs. 1, 8, ¶0021, ¶0032) and a drain region (e.g., 16, on the left side of WL1) disposed in the cell region (M) and another source region (e.g., 18, on the right side of WL2) and another drain region (e.g., 18, on the left side of WL2) disposed in the peripheral region (L), wherein the source region and the drain region are disposed apart from each other and the another source region and the another drain region are disposed apart from each other within the substrate (10);
a plurality of contact plugs (20/22 and 24) (Lee, Figs. 1, 8, ¶0022, ¶0032), a first contact plug (20) being connected to the source region (16), a second contact plug (22) being connected to the drain region (16), a third contact plug (24) being connected to the another source region (18, on the right side of WL2), and a fourth contact plug (24) being connected to the another drain region (18, on the left side of WL2);
a first source metal (M1S) (Lee, Figs. 1, 8, ¶0025, ¶0032) connected to the first contact plug (20), a first drain metal (M1d) connected to the second contact plug (22), another first source metal (M1, on the right side of WL2) connected to the third contact plug (24), and another first drain metal (M1, on the left side of WL2) connected to the fourth contact plug (24), wherein the first source metal and the first drain metal are disposed apart from each other and the another first source metal and the another first drain metal are disposed apart from each other;
a pair of first lower vias (e.g., V1) (Lee, Fig. 8, ¶0026, ¶0032), wherein one of the pair of first lower vias (V1) is connected to the another first source metal (e.g., M1, on the right side of WL2) and another of the pair of first lower vias is connected to the another first drain metal (e.g., M1, on the left side of WL2) in the peripheral region (L);
a pair of first upper vias (e.g., V2) (Lee, Fig. 8, ¶0027, ¶0032), wherein one (e.g., V2, on the right side of WL2) of the pair of first upper vias is connected (e.g., through the metal M2) to an upper end of the one of the pair of first lower vias (V1) and another (e.g., V2, on the left side of WL2) of the pair of upper vias is connected (e.g., through the metal M2) to an upper end of the another of the pair of first lower vias in the peripheral region (L).
Further, Lee does not specifically disclose (1) a sidewall disposed at an end of each of the pair of first lower vias; (2) wherein the sidewall has a flat bottom surface and a curved upper surface.
Regarding (1), Kang teaches forming an integrated circuit (see the annotated Fig. 3 above) (Kang, Fig. 3, ¶0003, ¶0019-¶0024, ¶0031-¶0040, ¶0048-¶0050, ¶0052-¶0055, ¶0062-¶0064, ¶0071-¶0075) comprising a logic cell including field effect transistors and contact structures, wherein a ring-shaped conductive pattern (274/154) (Kang, Fig. 3, ¶0048, ¶0074-¶0075) including a sidewall is disposed at an end of each of the pair of lower vias (276/156) to surround the end, wherein the sidewall (274/154) has a conductive metal material (e.g., titanium (Ti)) (Kang, Fig. 3, ¶0048); wherein the sidewall (274/154) surrounds an upper outer surface of each of the pair of lower vias (276/156), to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lee by forming a ring-shaped conductive pattern including a sidewall surrounding an upper end of the via contact as taught by Kang to have the semiconductor device comprising: a sidewall disposed at an end of each of the pair of first lower vias, in order to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075, ¶0147).
Regarding (2), Li teaches forming a protective structure (Li, Fig. 5A, ¶0017, ¶0025-¶0032, ¶0037) having a ring shape and including a sidewall (e.g., uppermost ring formed in the dielectric layer 106g) disposed on an outer sidewalls of the via structure (112), wherein the sidewall (Li, Fig. 5A, ¶0032, ¶0037) has a flat bottom surface and a curved upper surface (e.g., stepped surface of the uppermost ring), to protect adjacent dielectric layers, and to provide reliable connection structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the stacked via structure of Lee by forming a ring-shaped conductive pattern including a sidewall having a specific shape and surrounding an upper end of the via contact as taught by Li to have the stacked via structure, wherein the sidewall has a flat bottom surface and a curved upper surface, in order to protect adjacent dielectric layers, and to provide reliable connection structure (Li, ¶0017, ¶0030-¶0032, ¶0037).
Regarding claim 7, Lee in view of Kang and Li discloses the semiconductor device of claim 6. Further, Lee discloses the semiconductor device, further comprising: a second lower via (V1d) (Lee, Fig. 8, ¶0025-¶0027) connected to the first drain metal (M1d) in the cell region (M); a memory cell (MTJ) connected (e.g., through the metal M2d and plug W) to an upper part of the second lower via (V1d) in the cell region (M); and a second upper via (V3d) connected to an upper side of the memory cell (MTJ) in the cell region (M).
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0143214 to Lee in view of Kang (US 2023/0178476) and Li (US 2022/0223498) as applied to claim 7, and further in view of Chen et al. (US 2022/0216106, hereafter Chen).
Regarding claims 8, 11 and 12, Lee in view of Kang and Li discloses the semiconductor device of claim 6. Further, Lee does not specifically disclose the semiconductor device, wherein the memory cell comprises: a lower electrode connected to the upper part of the second lower via; a switching layer disposed on the lower electrode; an upper electrode disposed on the switching layer; and an insulation film layer disposed on the upper electrode (as claimed in claim 8); wherein the lower electrode has a bottom surface that has a width larger than a width of a top surface of the second lower via (as claimed in claim 11); wherein the upper electrode has a top surface that has a width larger than a width of a bottom surface of the second upper via (as claimed in claim 12).
However, Chen teaches forming a memory device (Chen, Fig. 5A, 14, ¶0001, ¶0023- ¶0024, ¶0029-¶0038, ¶0045-¶0053, ¶0067-¶0068) comprising an array of memory cells each including a resistive switching element capable of switching between high and low states, wherein the memory cell comprises: a lower electrode (132) (Chen, Fig. 5A, 14, ¶0029, ¶0045) connected to the upper part of the second lower via (106v); a switching layer (142) disposed on the lower electrode (132); an upper electrode (162) disposed on the switching layer (142); and an insulation film layer (e.g., one of the insulation layers 170) disposed on the upper electrode (162); wherein the lower electrode (132) has a bottom surface that has a width larger than a width of a top surface of the second lower via (106v); and wherein the upper electrode (162) has a top surface that has a width larger than a width of a bottom surface of the second upper via (180MV) (Chen, Fig. 5A, 14, ¶0053).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lee/Kang/Li by forming a resistive switching element capable of switching between high and low states as taught by Chen to have the semiconductor device, wherein the memory cell comprises: a lower electrode connected to the upper part of the second lower via; a switching layer disposed on the lower electrode; an upper electrode disposed on the switching layer; and an insulation film layer disposed on the upper electrode (as claimed in claim 8); wherein the lower electrode has a bottom surface that has a width larger than a width of a top surface of the second lower via (as claimed in claim 11); wherein the upper electrode has a top surface that has a width larger than a width of a bottom surface of the second upper via (as claimed in claim 12), in order to provide advanced resistive random access memory having reliable connections (Chen, ¶0001, ¶0023- ¶0024, ¶0045, ¶0053, ¶0067-¶0068).
Regarding claims 9-10 and 13, Lee in view of Kang, Li, and Chen discloses the semiconductor device of claim 8. Further, Lee does not specifically disclose the semiconductor device, wherein the sidewall is disposed at an upper end of each of the pair of first lower vias or at an upper end of the second lower via, the sidewall surrounding the upper end of each of the pair of first lower vias or the upper end of the second lower via (as claimed in claim 9); wherein the sidewall has a conductive metal material (as claimed in claim 10); wherein the sidewall has an upper surface configured to contact a bottom surface of each of the pair of first upper vias (as claimed in claim 13).
However, Kang teaches forming a ring-shaped conductive pattern (274/154) (Kang, Fig. 3, ¶0048, ¶0074-¶0075) including a sidewall is disposed at an end of each of the pair of lower vias (e.g., 156/276) to surround the end, wherein the sidewall (e.g., 274/154) has a conductive metal material (e.g., titanium (Ti)) (Kang, Fig. 3, ¶0048); wherein the sidewall (e.g., 274/154) is disposed at an upper end of each of the pair of first lower vias (e.g., 156/276), the sidewall (274/154) surrounding the upper end of each of the pair of first lower vias (e.g., 156/276), and wherein the sidewall (e.g., 154) has an upper surface configured to contact a bottom surface of each of the pair of first upper vias (CAV2), to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Lee/Kang/Li/Chen by forming a ring-shaped conductive pattern including a sidewall surrounding an upper end of the via contact as taught by Kang to have the semiconductor device, wherein the sidewall is disposed at an upper end of each of the pair of first lower vias or at an upper end of the second lower via, the sidewall surrounding the upper end of each of the pair of first lower vias or the upper end of the second lower via (as claimed in claim 9); wherein the sidewall has a conductive metal material (as claimed in claim 10); wherein the sidewall has an upper surface configured to contact a bottom surface of each of the pair of first upper vias (as claimed in claim 13), in order to physically fix the conductive plug/via inside the source/drain contact hole to improve electrical characteristics and reliability of the integrated circuit having reduced size (Kang, ¶0003, ¶0062, ¶0064, ¶0074-¶0075, ¶0147).
Response to Arguments
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
In response to Applicant's arguments that “Li cannot possibly disclose the curved upper surface of the alleged sidewall, because Li strictly utilizes lithography with a "hard mask" to form this structure shown in FIG. 5A of Li… This would typically yield a vertical outer sidewall profile-essentially a blocky, rectangular, or step-like cross-section with a relatively flat top surface, rather than a curved upper surface”, the examiner submits that “step-like cross-section” is a plane, and “a plane” does not have a top surface (flat or curved). Further, the patentability of a product does not depend on its method of production. If the product is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In the instant case, the method of production of conductive sidewall of Li is not relevant to the patentability of a product comprising a sidewall having a curved upper surface. The term ”a curved surface” is interpreted as a broad term that includes a curved out surface (convex surface), curved in surface (concave surface), or a surface of other curved shape (not flat). However, the invention (e.g., Fig. 16) shows a sidewall having a curved out (convex) upper surface, that is differs from the sidewall of Li having curved upper surface of step-like shape. Thus, further amendment of claim 1 (claim 6) to specify the curved surface as a convex (curved out) upper surface would be required to overcome the current rejection of claim 1 (claim 6).
Thus, the above applicant’s arguments are not persuasive, and the rejection of claim 1 (claim 6) under 35 USC 103 over Lee in view of Kang and Li is maintained.
Regarding dependent claims 2-4 and 7-13 which depend on the independent claims 1 and 6, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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