DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 2024/0321759 A1 hereinafter referred to as “Wang”).
With respect to claim 1, Wang discloses, in Figs.1-10, a tile for embedding components into a package substrate of a semiconductor device, the tile comprising: a plurality of passive devices (200, 240), at least two of the passive devices (200, 240) being individually packaged for surface mounting on first sides/(interface between devices 200, 240 and RDL 21) thereof and having respective second sides/(interface between devices 200, 240 and RDL 23) opposite the first sides, the first sides of the at least two passive devices (200, 240) being aligned, the second sides of the at least two passive devices (200, 240) being at different heights relative to the aligned first sides (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); the molding material layer 227 may be formed around the LSI die 200 in the x-direction and y-direction; see Par.[0060] wherein one or more integrated passive devices (IPDs) (not shown) may be connected to the back-side RDL interposer portion 21 and located in the lower molding layer 27 of the lower molded structure 10; see Fig.3J wherein the height of iVRs 240 is greater than that of LSI 200); and a polymer layer (229, 329) surrounding the at least two passive devices (200, 240) and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material).
With respect to claim 2, Wang discloses, in Figs.1-10, the tile, further comprising one or more first metal routing layers (23) by which metal terminals on the first sides of the at least two passive devices are electrically connected to metal terminals on a first outer surface of the tile (see Par.[0076]-[0078] wherein mthe front-side RDL interposer portion 23, for example, by flip-chip bonding using a plurality of connectors such as microbumps 128; the connectors may additionally or alternatively include solder balls, C4 bumps, etc; the microbumps 128 may be similar to the microbumps 28, microbumps 228 and microbumps 328 described above; the first semiconductor dies 141 may be electrically coupled to the LSI die 200 through the microbumps 128, the redistribution layers 12a in the front-side RDL interposer portion 23 and the microbumps 228 in the molded interposer portion 22; see Par.[0111]-[0112] wherein a metal seed layer 206a may be formed on the front-side RDL interposer portion 23 by a deposition and photolithographic process. In particular, the metal seed layer 206a may be deposited (e.g., by CVD, PVD or other suitable deposition process) on the uppermost dielectric layer 12).
With respect to claim 3, Wang discloses, in Figs.1-10, the tile, further comprising one or more second metal routing layers (21) by which metal terminals (228) on the second sides of the at least two passive devices are electrically connected to metal terminals on a second outer surface of the tile opposite the first, the one or more second metal routing layers being electrically connected to the metal terminals on the second sides of one or more of the at least two passive devices by way of one or more conductive vias formed in the polymer layer (see Par.[0076]-[0078] wherein mthe front-side RDL interposer portion 23, for example, by flip-chip bonding using a plurality of connectors such as microbumps 128; the connectors may additionally or alternatively include solder balls, C4 bumps, etc; the microbumps 128 may be similar to the microbumps 28, microbumps 228 and microbumps 328 described above; the first semiconductor dies 141 may be electrically coupled to the LSI die 200 through the microbumps 128, the redistribution layers 12a in the front-side RDL interposer portion 23 and the microbumps 228 in the molded interposer portion 22; see Par.[0111]-[0112] wherein a metal seed layer 206a may be formed on the front-side RDL interposer portion 23 by a deposition and photolithographic process. In particular, the metal seed layer 206a may be deposited (e.g., by CVD, PVD or other suitable deposition process) on the uppermost dielectric layer 12).
With respect to claim 4, Wang discloses, in Figs.1-10, the tile, further comprising one or more metal routing layers (21, 23) by which metal terminals on the second sides of the at least two passive devices are electrically connected to metal terminals on an outer surface of the tile, the one or more metal routing layers being electrically connected to the metal terminals on the second sides of one or more of the at least two passive devices by way of one or more conductive vias formed in the polymer layer (see Par.[0076]-[0078] wherein mthe front-side RDL interposer portion 23, for example, by flip-chip bonding using a plurality of connectors such as microbumps 128; the connectors may additionally or alternatively include solder balls, C4 bumps, etc; the microbumps 128 may be similar to the microbumps 28, microbumps 228 and microbumps 328 described above; the first semiconductor dies 141 may be electrically coupled to the LSI die 200 through the microbumps 128, the redistribution layers 12a in the front-side RDL interposer portion 23 and the microbumps 228 in the molded interposer portion 22; see Par.[0111]-[0112] wherein a metal seed layer 206a may be formed on the front-side RDL interposer portion 23 by a deposition and photolithographic process. In particular, the metal seed layer 206a may be deposited (e.g., by CVD, PVD or other suitable deposition process) on the uppermost dielectric layer 12).
With respect to claim 5, Wang discloses, in Figs.1-10, the tile, further comprising a frame (227) containing the plurality of passive devices (200, 240) and the polymer layer (see Par.[0062]-[0063] wherein the molding material layer 227 may include an added material (e.g., filler material) for improving a property of the molding material layer 227 (e.g., thermal conductivity, CTE, etc.)).
With respect to claim 6, Wang discloses, in Figs.1-10, the tile, wherein a conductive via (206) is formed within the frame (227) electrically connecting a metal terminal on a first outer surface of the tile to a metal terminal on a second outer surface of the tile opposite the first (see Par.[0070] wherein one or more through vias (TVs) 206 in the molding material layer 227. The TVs 206 may connect the front-side RDL interposer portion 23 to the redistribution layers 12a in the back-side RDL interposer portion 21. The TVs 206 may include, for example, one or more layers and may include metals, metal alloys, and/or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.)).
With respect to claim 7, Wang discloses, in Figs.1-10, the tile, wherein a conductive via is formed within the polymer layer electrically connecting a metal terminal on a first outer surface of the tile to a metal terminal on a second outer surface of the tile opposite the first (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge; see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material).
With respect to claim 8, Wang discloses, in Figs.1-10, the tile, wherein the plurality of passive devices includes stacked passive devices (see Fig.3L for stcked of packaging devices).
With respect to claim 9, Wang discloses, in Figs.1-10, the tile, further comprising a lead frame (100) on which the at least two passive devices are mounted (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20; see Par.[0133]-[0136] wherein all of the substrate portions 110 including the substrate portions 110A, 110B and 110C may be mounted concurrently on the back-side RDL interposer portion 21 of the interposer 20 in the same process; the substrate portions 110 may be connected to the back-side RDL interposer portion 21 by solder regions/joints (e.g., microbumps, C4 bumps, etc.) prior to mounting the the components 41 and connectors 42).
With respect to claim 10, Wang discloses, in Figs.1-10, the tile, further comprising a printed circuit board (PCB) on which the at least two passive devices are mounted (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 11, Wang discloses, in Figs.1-10, the tile, further comprising one or more first metal routing layers by which metal terminals on the first sides of the at least two passive devices are electrically connected to metal terminals on a first outer surface of the tile by way of one or more conductive vias formed in the PCB (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 12, Wang discloses, in Figs.1-10, the tile, further comprising one or more second metal routing layers (21, 23) by which metal terminals on the second sides of the at least two passive devices are electrically connected to metal terminals on a second outer surface of the tile opposite the first, the one or more second metal routing layers being electrically connected to the metal terminals on the second sides of one or more of the at least two passive devices by way of one or more conductive vias formed in the polymer layer (see Par.[0076]-[0078] wherein mthe front-side RDL interposer portion 23, for example, by flip-chip bonding using a plurality of connectors such as microbumps 128; the connectors may additionally or alternatively include solder balls, C4 bumps, etc; the microbumps 128 may be similar to the microbumps 28, microbumps 228 and microbumps 328 described above; the first semiconductor dies 141 may be electrically coupled to the LSI die 200 through the microbumps 128, the redistribution layers 12a in the front-side RDL interposer portion 23 and the microbumps 228 in the molded interposer portion 22; see Par.[0111]-[0112] wherein a metal seed layer 206a may be formed on the front-side RDL interposer portion 23 by a deposition and photolithographic process. In particular, the metal seed layer 206a may be deposited (e.g., by CVD, PVD or other suitable deposition process) on the uppermost dielectric layer 12).
With respect to claim 13, Wang discloses, in Figs.1-10, the tile, wherein the plurality of passive devices includes one or more passive devices embedded in the PCB (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 14, Wang discloses, in Figs.1-10, the tile, wherein a conductive via is formed within the PCB electrically connecting opposing sides of the PCB (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 15, Wang discloses, in Figs.1-10, the tile, further comprising a frame containing the plurality of passive devices, the polymer layer, and the PCB (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 16, Wang discloses, in Figs.1-10, the tile, wherein a conductive via (206) is formed within the frame (227) electrically connecting a metal terminal on a first outer surface of the tile to a metal terminal on a second outer surface of the tile opposite the first (see Par.[0157]-[0158] wherein the package structure 100 having the fourth alternative design may further include one or more conductors 1020 (e.g., metal wire, cable, non-wire connector, etc,) configured to electrically connect the package structure 100 to an external device such as a printed circuit board (PCB); the interposer 20 and including a lower molding layer 27 and a substrate portion 110A, 110B, 110C in the lower molding layer 27, wherein the substrate portion 110A, 110B, 110C may include conductive layers 114b, 116b electrically coupled to the semiconductor die 141 through the interposer 20).
With respect to claim 17, Wang discloses, in Figs.1-10, a package substrate of a semiconductor device, the package substrate comprising: a substrate core (10/100) (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110. Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110); and a tile embedded in the substrate core (100), the tile including: a plurality of passive devices (200, 240), at least two of the passive devices being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); and a polymer layer (229, 329) surrounding the plurality of passive devices and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material; see Fig.3L wherein upper surface areas of 200, 240 are surrounded by underfill polymer 229, 329 respectively).
With respect to claim 18, Wang discloses, in Figs.1-10, the package substrate, wherein a thickness of the tile matches a thickness of the substrate core (10/100) (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110. Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110).
With respect to claim 19, Wang discloses, in Figs.1-10, the package substrate, wherein the plurality of passive devices define a plurality of decoupling capacitors in relation to an integrated circuit to be mounted on the package substrate (see Par.[0060] wherein the IPDs may include one or more electronic components such as resistors, capacitors, inductors, coils, chokes, microstriplines, impedance matching elements, baluns, etc; the IPDs may be electrically coupled to the first semiconductor dies 141 through the back-side RDL interposer portion 21).
With respect to claim 20, Wang discloses, in Figs.1-10, the package substrate, wherein the plurality of passive devices define an integrated voltage regulator (IVR) in relation to an integrated circuit to be mounted on the package substrate (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge).
With respect to claim 21, Wang discloses, in Figs.1-10, a tile grid for manufacturing a plurality of tiles for embedding components (200, 240) into a package substrate (10/100) of a semiconductor device, the tile grid comprising: a frame (227) having a plurality of cutout regions defining a plurality of cells, each of the cells containing a plurality of passive devices (200, 240) (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge; see Par.[0062]-[0063] wherein the molding material layer 227 may include an added material (e.g., filler material) for improving a property of the molding material layer 227 (e.g., thermal conductivity, CTE, etc.)); and a plurality of polymer layers (229, 329) respectively filling the plurality of cells, each of the polymer layers surrounding the respective plurality of passive devices and having a planar surface (see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material; see Fig.3L wherein upper surface areas of 200, 240 are surrounded by underfill polymer 229, 329 respectively).
With respect to claim 22, Wang discloses, in Figs.1-10, the tile grid, wherein, in each of the cells, at least two of the passive devices (200, 240) are individually packaged for surface mounting on first sides thereof and have respective second sides opposite the first sides, the first sides of the at least two passive devices (200, 240) being aligned, the second sides of the at least two passive devices (200, 240) being at different heights relative to the aligned first sides, and, in each of the cells, the planar surface of the polymer layer is at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110. Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110; see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); the molding material layer 227 may be formed around the LSI die 200 in the x-direction and y-direction; see Par.[0060] wherein one or more integrated passive devices (IPDs) (not shown) may be connected to the back-side RDL interposer portion 21 and located in the lower molding layer 27 of the lower molded structure 10; see Fig.3J wherein the height of iVRs 240 is greater than that of LSI 200).
With respect to claim 23, Wang discloses, in Figs.1-10, the tile grid, wherein, in each of the cells, the plurality of passive devices includes a stack of two or more unpackaged capacitors (see Par.[0060] wherein the IPDs may include one or more electronic components such as resistors, capacitors, inductors, coils, chokes, microstriplines, impedance matching elements, baluns, etc; the IPDs may be electrically coupled to the first semiconductor dies 141 through the back-side RDL interposer portion 21; see Fig.3L for stcked of packaging devices).
With respect to claim 24, Wang discloses, in Figs.1-10, the tile grid, wherein each of the cells further contains a plurality of metal terminals, the plurality of metal terminals including: two or more first metal terminals electrically isolated from each other and electrically connected to respective first electrodes of the two or more unpackaged capacitors; and a shared second metal terminal electrically connected to the second electrodes of the two or more unpackaged capacitors (see Par.[0070] wherein one or more through vias (TVs) 206 in the molding material layer 227. The TVs 206 may connect the front-side RDL interposer portion 23 to the redistribution layers 12a in the back-side RDL interposer portion 21. The TVs 206 may include, for example, one or more layers and may include metals, metal alloys, and/or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.)).
With respect to claim 25, Wang discloses, in Figs.1-10, a method of manufacturing a tile for embedding components into a package substrate of a semiconductor device, the method comprising: surrounding at least two passive devices (200, 240) with a polymer layer (229, 329), the at least two passive devices (200, 240) being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides, the polymer layer (229, 329) having a planar surface at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); the molding material layer 227 may be formed around the LSI die 200 in the x-direction and y-direction; see Par.[0060] wherein one or more integrated passive devices (IPDs) (not shown) may be connected to the back-side RDL interposer portion 21 and located in the lower molding layer 27 of the lower molded structure 10; see Fig.3J wherein the height of iVRs 240 is greater than that of LSI 200; see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material); and singulating a tile comprising the polymer layer and a plurality of passive devices including the at least two passive devices (see Par.[0093], [0151], [0153] wherein the substrate portions 110A, 110B and 110C may be cut (e.g., by dicing) and arranged so as to account for most of the substantially planar lower surface S1).
Claims 1-2, 5-6, 9-11, 13-19, 21-22, 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2016/0336296 A1 hereinafter referred to as “Jeong”).
With respect to claim 1, Jeong discloses, in Figs.1-29, A tile for embedding components into a package substrate of a semiconductor device, the tile comprising: a plurality of passive devices (124, 120), at least two of the passive devices (120, 124) being individually packaged for surface mounting on first sides/(lower surface) thereof and having respective second sides/(upper surface) opposite the first sides, the first sides of the at least two passive devices (120, 124) being aligned, the second sides of the at least two passive devices (120, 124) being at different heights relative to the aligned first sides (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown); and a polymer layer (150) surrounding the at least two passive devices (120, 124) and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used).
With respect to claim 2, Jeong discloses, in Figs.1-29, the tile, further comprising one or more first metal routing layers (130, 140) by which metal terminals (120P) on the first sides of the at least two passive devices are electrically connected to metal terminals on a first outer surface of the tile (see Par.[0073]-[0074] wherein the electronic component package 100A according to an example may further include an outer layer 160 disposed below the redistribution parts 130 and 140; see Par.[0058]-[0059] wherein he purpose of the electrode pad 120P may be to electrically connect the electronic component 120 externally, and a material of the electrode pad 120P is not particularly limited as long as it is a conductive material. For example, the conductive material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pd), or alloys thereof, but is not limited thereto).
With respect to claim 5, Jeong discloses, in Figs.1-29, the tile, further comprising a frame (110) containing the plurality of passive devices and the polymer layer (see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed).
With respect to claim 6, Jeong discloses, in Figs.1-29, the tile, wherein a conductive via (110Y, 113) is formed within the frame (110) electrically connecting a metal terminal on a first outer surface of the tile to a metal terminal on a second outer surface of the tile opposite the first (see Par.[0110] wherein the through-holes 110Y may be designed depending on a size, a shape, the number, or the like, of target through-wiring 113 to be formed; a of FIG. 15B is a plan view of the frame 110 in which the through-holes 110X and the through-holes 110Y are formed, and B of FIG. 15B illustrates a cross section of a partial region that may be utilized as a unit package in A of FIG. 15B).
With respect to claim 9, Jeong discloses, in Figs.1-29, the tile, further comprising a lead frame on which the at least two passive devices are mounted (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown).
With respect to claim 10, Jeong discloses, in Figs.1-29, the tile, further comprising a printed circuit board (PCB) on which the at least two passive devices are mounted (see Par.[0040], [0044], [0046], [0075] wherein chip related components 1020, network related components 1030, other components 1040, and the like, may be physically and/or electrically connected to the mother board 1010 (e.g.; PCB)).
With respect to claim 11, Jeong discloses, in Figs.1-29, the tile, further comprising one or more first metal routing layers by which metal terminals on the first sides of the at least two passive devices are electrically connected to metal terminals on a first outer surface of the tile by way of one or more conductive vias formed in the PCB (see Par.[0040], [0044], [0046], [0075] wherein chip related components 1020, network related components 1030, other components 1040, and the like, may be physically and/or electrically connected to the mother board 1010 (e.g.; PCB)).
With respect to claim 13, Jeong discloses, in Figs.1-29, the tile, wherein the plurality of passive devices includes one or more passive devices embedded in the PCB (see Par.[0040], [0044], [0046], [0075] wherein chip related components 1020, network related components 1030, other components 1040, and the like, may be physically and/or electrically connected to the mother board 1010 (e.g.; PCB)).
With respect to claim 14, Jeong discloses, in Figs.1-29, the tile, wherein a conductive via is formed within the PCB electrically connecting opposing sides of the PCB (see Par.[0040], [0044], [0046], [0075] wherein chip related components 1020, network related components 1030, other components 1040, and the like, may be physically and/or electrically connected to the mother board 1010 (e.g.; PCB)).
With respect to claim 15, Jeong discloses, in Figs.1-29, the tile, further comprising a frame containing the plurality of passive devices, the polymer layer, and the PCB (see Par.[0040], [0044], [0046], [0075] wherein chip related components 1020, network related components 1030, other components 1040, and the like, may be physically and/or electrically connected to the mother board 1010 (e.g.; PCB)).
With respect to claim 16, Jeong discloses, in Figs.1-29, the tile, wherein a conductive via is formed within the frame electrically connecting a metal terminal on a first outer surface of the tile to a metal terminal on a second outer surface of the tile opposite the first (see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed).
With respect to claim 17, Jeong discloses, in Figs.1-29, a package substrate of a semiconductor device, the package substrate comprising: a substrate core; and a tile embedded in the substrate core, the tile including: a plurality of passive devices (120, 124), at least two of the passive devices (120, 124) being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown); and a polymer layer (150) surrounding the plurality of passive devices and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used).
With respect to claim 18, Jeong discloses, in Figs.1-29, the package substrate, wherein a thickness of the tile matches a thickness of the substrate core (see Figs.24-25).
With respect to claim 19, Jeong discloses, in Figs.1-29, the package substrate, wherein the plurality of passive devices define a plurality of decoupling capacitors in relation to an integrated circuit to be mounted on the package substrate (see Par.[0043] wherein other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-firing ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), and the like).
With respect to claim 21, Jeong discloses, in Figs.1-29, a tile grid for manufacturing a plurality of tiles for embedding components into a package substrate of a semiconductor device, the tile grid comprising: a frame (110) having a plurality of cutout regions defining a plurality of cells, each of the cells containing a plurality of passive devices (124, 120) (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown; see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed); and a plurality of polymer layers (150) respectively filling the plurality of cells, each of the polymer layers surrounding the respective plurality of passive devices and having a planar surface (see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used).
With respect to claim 22, Jeong discloses, in Figs.1-29, the tile grid, wherein, in each of the cells, at least two of the passive devices are individually packaged for surface mounting on first sides thereof and have respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides, and, in each of the cells, the planar surface of the polymer layer is at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown; see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed).
With respect to claim 25, Jeong discloses, in Figs.1-29, a method of manufacturing a tile for embedding components into a package substrate of a semiconductor device, the method comprising: surrounding at least two passive devices (124, 120) with a polymer layer (150), the at least two passive devices being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides, the polymer layer having a planar surface at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown; see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed; see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used); and singulating a tile comprising the polymer layer and a plurality of passive devices including the at least two passive devices (see Par.[0080] wherein the plurality of electronic component packages 100A may be singulated into individual unit packages through a sawing process).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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