DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4 – 7, 9 – 10, 15 and 17 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onuki et al. (US 2020/0402577).
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(Claim 1) Onuki et al. teach a display apparatus comprising:
a substrate (fig. 28 #231);
a buffer layer (511, paragraph 430) located on the substrate;
a first thin-film transistor (paragraph 353) located on the buffer layer, the first thin-film transistor comprising a first semiconductor layer (530) and a first gate electrode (560) insulated from the first semiconductor layer,
the first semiconductor layer (530) comprising an oxide semiconductor (paragraph 46); and
a first inorganic insulating layer (550) located between the first semiconductor layer (530) and the first gate electrode (560),
wherein a side surface of the first inorganic insulating layer (550) is disposed between the first semiconductor layer (530) and the first gate electrode (560) in a direction perpendicular (vertical direction) to the substrate,
wherein a hydrogen (H2) emission amount of the first inorganic insulating layer is at least 1 x 10E19 mole/cm3 (paragraph 359).
(Claim 2) Onuki et al. teach wherein a nitrogen oxide (NOx) emission amount of the first inorganic insulating layer is no higher than 1 x 10E19 mole/cm3 (paragraph 365).
(Claim 4) Onuki et al. teach wherein the first inorganic insulating layer comprises silicon oxide (SiOx, paragraph 357).
(Claim 5) Onuki et al. teach wherein a hydrogen (H2) emission amount of the buffer layer is at least 3 x 10E19 mole/cm3 (paragraph 359).
(Claim 6) Onuki et al. teach wherein a hydrogen (H2) concentration in the buffer layer is no higher than 8 x 10E20 atom/cm3 (paragraph 35).
(Claim 7) Onuki et al. teach wherein the buffer layer comprises one of silicon oxide (SiOx) and silicon nitride (SiNx) (paragraph 357).
(Claim 9) Onuki et al. teach wherein the first semiconductor layer comprises at least one of indium gallium zinc oxide (IGZO), indium tin gallium oxide (ITGO), indium tin gallium zinc oxide (ITGZO), indium tin oxide (ITO), indium gallium oxide (IGO), and indium zinc oxide (IZO) (paragraph 387).
(Claim 10) a method of manufacturing a display apparatus, the method comprising:
forming a buffer layer (511, paragraph 430) on a substrate;
forming, on the buffer layer, a first semiconductor layer (530) comprising an oxide semiconductor;
forming a first inorganic insulating layer (550) on the first semiconductor layer; and
forming a first gate electrode (560) on the first inorganic insulating layer (550) to form a first thin-film transistor comprising the first semiconductor layer (530) and the first gate electrode (560) insulated from the first semiconductor layer,
wherein a side surface of the first inorganic insulating layer (550) is disposed between the first semiconductor layer (530) and the first gate electrode (560) in a direction perpendicular (vertical direction) to the substrate,
wherein a hydrogen (H2) emission amount of the first inorganic insulating layer is at least 1 x 10E19 mole/cm3 (paragraph 357).
(Claim 15) Onuki et al. teach wherein the forming of the first semiconductor layer comprising the oxide semiconductor comprises performing a sputtering process (paragraphs 385 – 386),
wherein defects of a lower buffer layer due to plasma damage in the sputtering process are no higher than 8x 10E14 spins/cm2 (paragraphs 361 – 363; note the units cm2 to cm3).
(Claim 17) Onuki et al. teach wherein a nitrogen oxide (NOx) emission amount of the first inorganic insulating layer is no higher than 1 x 1019 mole/cm3 (paragraph 365).
(Claim 18) Onuki et al. teach wherein a hydrogen (H2) emission amount of the first inorganic insulating layer is at least 1 x 10E19 mole/cm3 (paragraph 359).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Onuki et al. (US 2020/0402577) in view of Ito et al. (US 2016/0329434).
(Claim 8) Onuki et al. lack wherein a thickness of the first semiconductor layer ranges from about 20 Å to about 400 Å.
However, Ito et al. teach wherein a thickness of the first semiconductor layer (fig. 1B #122) ranges from about 20 Å to about 400 Å (paragraph 270) for the benefit of stabilizing the electrical characteristics of a transistor (paragraph 269).
Therefore, it would have been obvious to one of ordinary skill in the art to incorporate the references for the benefit of stabilizing the electrical characteristics of a transistor.
(Claim 20) Onuki et al. lack wherein a thickness of the first semiconductor layer ranges from about 20 Å to about 400 Å.
However, Ito et al. teach wherein a thickness of the first semiconductor layer (fig. 1B #122) ranges from about 20 Å to about 400 Å (paragraph 270) for the benefit of stabilizing the electrical characteristics of a transistor (paragraph 269).
Therefore, it would have been obvious to one of ordinary skill in the art to incorporate the references for the benefit of stabilizing the electrical characteristics of a transistor.
Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Onuki et al. (US 2020/0402577) in view of Na et al. (US 2018/0061868)
(Claim 3) Onuki et al. lack wherein a thickness of the first inorganic insulating layer ranges from about 1000 Å to about 2000 Å.
However, Na et al. teach wherein a thickness of the first inorganic insulating layer (fig. 2 #213) ranges from about 1000 Å to about 2000 Å for the benefit of functioning as a gate insulating layer (paragraph 95).
Therefore, it would have been obvious to one of ordinary skill in the art to incorporate the references for the benefit of functioning as a gate insulating layer.
(Claim 19) Onuki et al. lack wherein a thickness of the first inorganic insulating layer ranges from about 1000 Å to about 2000 Å.
However, Na et al. teach wherein a thickness of the first inorganic insulating layer (fig. 2 #213) ranges from about 1000 Å to about 2000 Å for the benefit of functioning as a gate insulating layer (paragraph 95).
Therefore, it would have been obvious to one of ordinary skill in the art to incorporate the references for the benefit of functioning as a gate insulating layer.
Allowable Subject Matter
Claims 11 – 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on June 30, 2026 have been fully considered but they are not persuasive.
Applicant argues:
Onuki does not teach or suggest that a side surface of the first inorganic insulating layer is disposed between the first semiconductor layer and the first gate electrode in a direction perpendicular to the substrate. Instead in the implementations discussed throughout Onuki side surfaces of the alleged first inorganic insulating layer disposed on top of the of the alleged first semiconductor. For example, in Fig. 33B reprinted below for convenience. The alleged first insulating layer element 550 is located on top of and not between the alleged first semiconductor layer element 530 and the alleged first gate electrode element 560 in a direction perpendicular to the substrate.
Reply:
The first inorganic insulation layer (550) is disposed on top first semiconductor layer element 530.
The first gate electrode (560) is disposed on top of the first inorganic insulation layer (550).
Therefore, the first inorganic insulating layer (550) is disposed between the first semiconductor layer (530) and the first gate electrode (560) in the vertical direction which comprise the side surfaces and also perpendicular to substrate disposed in the x-y plane.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
September 4, 2026
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