DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on July 13, 2026.
Claims 1-20 are pending. Claims 1-3 and 11-12 are amended. Claims 1, 11 and 12 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the phrase “a monotonic stepped pass-voltage profile during the program operation” is unclear because the claim does not identify the variable with respect to which the profile is monotonic. It is unclear whether the limitation requires a spatial voltage distribution, a temporal sequence of voltages or an ordering of the three voltage magnitudes.
Claim 1, from which claim 2 depends, assigns the first pass voltage V1 to an unselected word line in the first memory deck, the third pass voltage V3 to the dummy word line at the junction, and the second pass voltage V2 to the word line in the second memory deck. Thus, considering these pass voltages in their physical order from the first deck through the junction to the second deck, the sequence is V1 => V3 => V2. Because V1 > V2 > V3, this sequence decreases and then increases, rather than varying monotonically.
Alternatively, if the claimed profile refers to voltage variation over time, neither the phrase “during the program operation” nor the recited voltage inequalities identifies a temporal sequence over which monotonicity is required.
Although claim 2 recites V1 > V2 > V3 that establish the relative voltage magnitude, it remains unclear whether the “monotonic stepped pass-voltage profile” only names that numerical relationship or additionally requires a spatial or temporal relationship.
Regarding claim 3, the additional limitation concerning the relative voltage differences and the expression V1 > V2 > V3 > VHEI do not resolve the foregoing ambiguity. They further specify voltage magnitudes but do not identify the variable over which the profile is monotonic.
Thus, the scope of the “monotonic stepped pass-voltage profile” limitation in claims 2 and 3 is unclear.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 20190043591) in view of Park et al. (US 20110090738; hereinafter “Park 738”) and Park et al. (US 20110305079; hereinafter “Park 079”).
Regarding independent claim 1, Fastow et al. disclose a memory device [Fig. 1: 100] comprising:
a memory cell array [Fig. 10: 1000] comprising a first memory deck [Fig. 10: 1040] and a second memory deck [Fig. 10: 1060] stacked with each other [see Fig. 10, para. 24 as well as para. 72], wherein the first memory deck and the second memory deck both comprise a plurality of memory cell layers and a word line layer corresponding to each memory cell layer [para. 22-24], and at least one dummy memory cell layer [Fig. 10: 1017, 1021, 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the first memory deck and the second memory deck [see Fig. 10, interface dummy WLs are provided on an internal boundary of a deck, here on either side of poly plug 1051, para. 73]; and
a peripheral circuit [Fig. 1: 116] coupled to the memory cell array [see Fig. 1, para. 35] and configured to:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84], apply a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and apply a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
apply a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92]; and
apply a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triggered.
Park 738 teaches a voltage (3V) applied to a dummy word line DWL that is lower than a voltage (8V) applied to non-selected word line while a program operation is performed [see Fig. 10, para. 53].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park 738 and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Park 738 and greater than a threshold voltage below which hot electron injection is triggered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to reduce the channel length of selection transistor, improve a program inhibit characteristic [see Park 738’s para. 44] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding claim 2, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. teach wherein a difference between the first pass voltage [Fig. 13: Vpass_sel] and the second pass voltage [Fig. 13: Vpass_unsel] is a first difference [Vpass_unsel may be 1-3V lower than Vpass_sel, para. 63].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and a difference between the second pass voltage and the third pass voltage is a second difference, wherein the first difference is different from the second difference, and wherein the first pass voltage, the second pass voltage, and the third pass voltage define a monotonic stepped pass- voltage profile during the program operation in which the first pass voltage is greater than the second pass voltage, the second pass voltage is greater than the third pass voltage, and the third pass voltage is greater than the threshold voltage below which hot electron injection is triggered.
Park 738 teaches a voltage (3V) applied to a dummy word line DWL that is lower than a voltage (8V) applied to non-selected word line while a program operation is performed [see Fig. 10, para. 53]. The difference between two voltages is 5V that is different from Fastow et al.’s first difference.
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park 738 and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Park 738 and greater than a threshold voltage below which hot electron injection is triqqered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to reduce the channel length of selection transistor, improve a program inhibit characteristic [see Park 738’s para. 44] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding claim 3, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 2.
Furthermore, Fastow et al. in combination with Park 738 and Park 079 teach wherein the second difference is greater than the first difference, wherein the monotonic stepped pass-voltage profile satisfies V1 > V2 > V3 > VHEI, where V1 is the first pass voltage, V2 is the second pass voltage, V3 is the third pass voltage, and VHEI is the threshold voltage below which hot electron injection is triggered [see the rejection of claim 2 above].
Regarding claim 4, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the plurality of memory cell layers in the second memory deck are in a programmed state [para. 83-84].
Regarding claim 5, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the peripheral circuit is configured to:
apply the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 6, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein
the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 7, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the at least one dummy memory cell layer and the dummy word line layer corresponding to each dummy memory cell layer at the junction position of the first memory deck and the second memory deck belong to at least one of the first memory deck or the second memory deck [see Fig. 10, para. 73].
Regarding claim 8, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 7.
Furthermore, Fastow et al. disclose wherein the at least one dummy word line layer at the junction position of the first memory deck and the second memory deck comprises a first dummy word line layer [Fig. 10: 1017] located in the first memory deck [Fig. 10: 1040] and a second dummy word line layer [Fig. 10: 1031] located in the second memory deck [Fig. 10: 1060, para. 72-73], and the third pass voltage comprises a third sub-pass voltage [Fig. 13: Vpass_int1] and a fourth sub-pass voltage [Fig. 13: Vpass_int2], wherein
the peripheral circuit is configured to apply the third sub-pass voltage [Fig. 13: Vpass_int1] to the first dummy word line layer [Fig. 13: 1317] and apply the fourth sub-pass voltage [Fig. 13: Vpass_int2] to the second dummy word line layer [Fig. 13: 1338], wherein the third sub-pass voltage is different from the fourth sub-pass voltage.
Regarding claim 10, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Regarding independent claim 11, Fastow et al. disclose a memory system comprising:
one or more memory devices [Fig. 1: 100], each of the memory devices comprising:
a memory cell array [Fig. 10: 1000] comprising a first memory deck [Fig. 10: 1040] and a second memory deck [Fig. 10: 1060] stacked with each other [see Fig. 10, para. 24 as well as para. 72], wherein the first memory deck and the second memory deck both comprise a plurality of memory cell layers and a word line layer corresponding to each memory cell layer [para. 22-24], and at least one dummy memory cell layer [Fig. 10: 1017, 1021, 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the first memory deck and the second memory deck [see Fig. 10, interface dummy WLs are provided on an internal boundary of a deck, here on either side of poly plug 1051, para. 73]; and
a peripheral circuit [Fig. 1: 116] coupled to the memory cell array [see Fig. 1, para. 35] and configured to:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84], apply a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and apply a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
apply a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92]; and
apply a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84], and
a memory controller [Fig. 17: 1724] coupled to the one or more memory devices [Fig. 17: 1712] and configured to control the one or more memory devices [para. 100].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triggered.
Park 738 teaches a voltage (3V) applied to a dummy word line DWL that is lower than a voltage (8V) applied to non-selected word line while a program operation is performed [see Fig. 10, para. 53].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park 738 and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Park 738 and greater than a threshold voltage below which hot electron injection is triggered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to reduce the channel length of selection transistor, improve a program inhibit characteristic [see Park 738’s para. 44] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding independent claim 12, Fastow et al. disclose an operation method of a memory device, comprising:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84] of a memory cell array [Fig. 10: 1000] of the memory device [Fig. 1: 100], applying a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and applying a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
applying a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92] which is stacked with the first memory deck [see Fig. 10, para. 24 as well as para. 72]; and
applying a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triggered.
Park 738 teaches a voltage (3V) applied to a dummy word line DWL that is lower than a voltage (8V) applied to non-selected word line while a program operation is performed [see Fig. 10, para. 53].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park 738 and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Park 738 and greater than a threshold voltage below which hot electron injection is triggered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to reduce the channel length of selection transistor, improve a program inhibit characteristic [see Park 738’s para. 44] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding claim 13, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the applying a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92] comprises:
applying the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 14, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein
the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 15, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the at least one dummy word line layer at the junction position of the first memory deck and the second memory deck comprises a first dummy word line layer [Fig. 10: 1017] located in the first memory deck [Fig. 10: 1040] and a second dummy word line layer [Fig. 10: 1031] located in the second memory deck [Fig. 10: 1060, para. 72-73], and the third pass voltage comprises a third sub-pass voltage [Fig. 13: Vpass_int1] and a fourth sub-pass voltage [Fig. 13: Vpass_int2], wherein
the applying a third pass voltage to a dummy word line layer corresponding to at least one dummy memory cell layer at a junction position of the first memory deck and the second memory deck comprises:
applying the third sub-pass voltage [Fig. 13: Vpass_int1] to the first dummy word line layer [Fig. 13: 1317] and applying the fourth sub-pass voltage [Fig. 13: Vpass_int2] to the second dummy word line layer [Fig. 13: 1338], wherein the third sub-pass voltage is different from the fourth sub-pass voltage.
Regarding claim 17, Fastow et al. in combination with Park 738 and Park 079 the limitation with respect to claim 14.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Regarding claim 18, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 11.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the peripheral circuit is configured to:
apply the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 19, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 11.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 20, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claim 11.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 20190043591) in view of Park et al. (US 20110090738; hereinafter “Park 738”) and Park et al. (US 20110305079; hereinafter “Park 079”) as applied to claims 1 and 12 above, and further in view of Rajagiri et al. (US 20240028253).
Regarding claims 9 and 16, Fastow et al. in combination with Park 738 and Park 079 teach the limitation with respect to claims 1 and 12.
However, Fastow et al. in combination with Park 738 and Park 079 are silent with respect to the peripheral circuit is configured to:
when performing a program operation on the plurality of memory cell layers in the first memory deck, perform one of a sequential program operation or a reversed program operation on the plurality of memory cell layers in the first memory deck.
Rajagiri et al. teach a NAND string can be programmed from source-to-drain and in a drain-to-source configuration, i.e., both normal and reverse word line order [para. 56-57].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Rajagiri et al. to the teaching of Fastow et al. in combination with Park 738 and Park 079 such that implementing the deck programming as taught by Fastow et al. in combination with Park 738 and Park 079 to select either sequential or reversed program operation within the deck during program as taught by Rajagiri et al. to lower the lateral gradient and mitigate the hot-electron injection phenomenon [see Rajagiri et al.’s para. 17-19].
Response to Arguments
The applicant has amended independent claims 1 and 11-12 that are similar to claims filed on November 17, 2025. Therefore, the Examiner has rejected claims 1-8, 10-15 and 17-20 under 35 U.S.C. § 103 as being unpatentable over Fastow et al. (US 20190043591) in view of Park et al. (US 20110090738; hereinafter “Park 738”) and Park et al. (US 20110305079; hereinafter “Park 079”) and rejected claims 9 and 16 as being unpatentable over Fastow et al. in view of Park 738, Park 079 and further in view of Rajagiri et al. (US 20240028253). These rejections are applied in Final Rejection of January 27, 2026.
Applicant's argument filed on July 13, 2026 with respect to independent claims 1, 11 and 12 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that Fastow discloses the third pass voltage (Vpass_int1, Vpassint2) as "equal or greater than the first pass voltage [Vpasssel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61]." Fastow's teaching that the interface dummy word line voltage should be equal to or greater than the first pass voltage is diametrically opposed to the claimed relationship (Vpass3 < Vpass2 < Vpass1). Applicant also asserts that “a person of ordinary skill in the art reading Fastow would be taught away from reducing the interface word line voltage below the second pass voltage, because doing so would, under Fastow's framework, reduce pillar boosting rather than increase it. Thus, the motivation the Office Action offers to modify Fastow is contradicted by Fastow's own teachings and purpose”, see Applicant's Remarks pages 11-12. This particular remark is not considered persuasive.
Although Fastow et al. disclose, in an embodiment, the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] is equal or greater than the first pass voltage [Fig. 13: Vpass_sel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61], Fastow et al. do not state that lower interface dummy word line voltage is unsuitable or prohibited under all programming conditions. Fastow et al. state the disclosed voltage values as exemplary and recognize independent selection of interface dummy biases to manage inter-deck electrical conditions [para. 53-57]. The disclosure of a preferred alternative does not necessarily constitute teaching away unless the reference criticizes, discredits, or otherwise discourages investigation of the claimed alternative.
More importantly, the rejection is based on the combined teachings of Fastow et al., Park 738 and Park 079, rather than Fastow et al. alone. Park 738 teaches a voltage (3V) applied to a dummy word line DWL that is lower than a voltage (8V) applied to non-selected word line while a program operation is performed [see Fig. 10, para. 53]. Park 079 explains controlling the dummy word line voltage in this manner reduces leakage and reduces hot electron injection [para. 42-44]. Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49]. A person having ordinary skill in the art before the effective filling date of claimed invention would have found it obvious to apply teachings of Park 738 and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Park 738 and greater than a threshold voltage below which hot electron injection is triggered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to improve a program inhibit characteristic [see Park 738’s para. 44] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47]. The modification would not change Fastow et al.’s principle of operation. Fastow et al. would continue to program one deck while inhibiting another through independently controlled word line bias voltages. This modification only changes the magnitude of a bias voltage that Fastow et al.’s existing circuitry already independently generates and applies to the interface dummy word lines.
Applicant’s arguments regarding to Chen reference have been considered but are moot because the new ground of rejection does not rely on Chen reference for any teaching or matter specifically challenged in the argument.
For the above reasons, the previously applied rejection is considered proper and maintained. The independent claims 11 and 12 were argued for substantially the same reason, and the arguments are not persuasive for the same reason.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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