DETAILED ACTION
This action is responsive to the following communications: the Request for Continued Examination (with claim amendment) filed on March 30, 2026.
Claims 1-20 are pending. Claims 1, 11 and 12 are amended. Claims 1, 11 and 12 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/30/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 20190043591) and in view of Chen et al. (US 10438671) and Park et al. (US 20110305079; hereinafter “Park 079”).
Regarding independent claim 1, Fastow et al. disclose a memory device [Fig. 1: 100] comprising:
a memory cell array [Fig. 10: 1000] comprising a first memory deck [Fig. 10: 1040] and a second memory deck [Fig. 10: 1060] stacked with each other [see Fig. 10, para. 24 as well as para. 72], wherein the first memory deck and the second memory deck both comprise a plurality of memory cell layers and a word line layer corresponding to each memory cell layer [para. 22-24], and at least one dummy memory cell layer [Fig. 10: 1017, 1021, 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the first memory deck and the second memory deck [see Fig. 10, interface dummy WLs are provided on an internal boundary of a deck, here on either side of poly plug 1051, para. 73]; and
a peripheral circuit [Fig. 1: 116] coupled to the memory cell array [see Fig. 1, para. 35] and configured to:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84], apply a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and apply a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
apply a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92]; and
apply a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triqqered and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck. Fastow et al. disclose the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] is equal or greater than the first pass voltage [Fig. 13: Vpass_sel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61].
Chen et al. teach a 0 V, or another relatively low turn-off voltage applied to the dummy word lines (e.g., WLDL and WLDU in FIG. 5) [Fig. 11A: step 1104b, col. 21, lines 39-42 as well as col. 15, lines 6-8] that is lower than the nominal pass voltage Vpass (8-10V) can be applied to the remaining non-interface unselected word lines (e.g., WL0-WL46 and WL49-WL95) while a program operation is performed [see Fig. 5 and Fig. 11A, col. 5, lines 37-40 as well as col. 21, lines 34-35, 55-57] and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck [see Fig. 5, the voltages of the interface unselected word lines (e.g., WLDL and WLDU in FIG. 5) are kept at a turn-off voltage such as 0 V throughout the program phase to block the residue electrons in the lower tier (Fig. 5: 600) from reaching the upper tier (Fig. 5: 601), col. 5, lines 27-30].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chen et al. and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Chen et al. and greater than a threshold voltage below which hot electron injection is triqqered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to block the residue electrons in the second deck from reaching the first deck, advantageously avoids any delay in the programming time [see Chen et al.’s col. 5, lines 29-42] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding claim 2, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 1.
Furthermore, Fastow et al. teach wherein a difference between the first pass voltage [Fig. 13: Vpass_sel] and the second pass voltage [Fig. 13: Vpass_unsel] is a first difference [Vpass_unsel may be 1-3V lower than Vpass_sel, para. 63]. Fastow et al. also disclose the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] is equal or greater than the first pass voltage [Fig. 13: Vpass_sel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and a difference between the second pass voltage and the third pass voltage is a second difference, wherein the first difference is different from the second difference.
Chen et al. teach a 0 V, or another relatively low turn-off voltage applied to the dummy word lines (e.g., WLDL and WLDU in FIG. 5) [Fig. 11A: step 1104b, col. 21, lines 39-42 as well as col. 15, lines 6-8] that is lower than the nominal pass voltage Vpass (8-10V) can be applied to the remaining non-interface unselected word lines (e.g., WL0-WL46 and WL49-WL95) while a program operation is performed [see Fig. 5 and Fig. 11A, col. 5, lines 37-40 as well as col. 21, lines 34-35, 55-57]. The difference between two voltages is about 8-10V that is different from Fastow et al.’s first difference.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chen et al. to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line while a program operation is performed as taught by Chen et al. into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck wherein the difference between these voltages above is different from the difference between the first pass voltage applied to a word line layer corresponding to an unselected memory cell layer in the first memory deck and the second pass voltage applied to the word line layer corresponding to the plurality of memory cell layers in the second memory deck to balance boosting and disturb at the junction and create a stronger barrier at the junction.
Regarding claim 3, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 2.
Furthermore, Fastow et al. in combination with Chen et al. teach the second difference is greater than the first difference [see the rejection of claim 2 above].
Regarding claim 4, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the plurality of memory cell layers in the second memory deck are in a programmed state [para. 83-84].
Regarding claim 5, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the peripheral circuit is configured to:
apply the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 6, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein
the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 7, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 1.
Furthermore, Fastow et al. disclose wherein the at least one dummy memory cell layer and the dummy word line layer corresponding to each dummy memory cell layer at the junction position of the first memory deck and the second memory deck belong to at least one of the first memory deck or the second memory deck [see Fig. 10, para. 73].
Regarding claim 8, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 7.
Furthermore, Fastow et al. disclose wherein the at least one dummy word line layer at the junction position of the first memory deck and the second memory deck comprises a first dummy word line layer [Fig. 10: 1017] located in the first memory deck [Fig. 10: 1040] and a second dummy word line layer [Fig. 10: 1031] located in the second memory deck [Fig. 10: 1060, para. 72-73], and the third pass voltage comprises a third sub-pass voltage [Fig. 13: Vpass_int1] and a fourth sub-pass voltage [Fig. 13: Vpass_int2], wherein
the peripheral circuit is configured to apply the third sub-pass voltage [Fig. 13: Vpass_int1] to the first dummy word line layer [Fig. 13: 1317] and apply the fourth sub-pass voltage [Fig. 13: Vpass_int2] to the second dummy word line layer [Fig. 13: 1338], wherein the third sub-pass voltage is different from the fourth sub-pass voltage.
Regarding claim 10, Fastow et al. in combination with Chen et al. and Park 079 teach the limitation with respect to claim 1.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Regarding independent claim 11, Fastow et al. disclose a memory system comprising:
one or more memory devices [Fig. 1: 100], each of the memory devices comprising:
a memory cell array [Fig. 10: 1000] comprising a first memory deck [Fig. 10: 1040] and a second memory deck [Fig. 10: 1060] stacked with each other [see Fig. 10, para. 24 as well as para. 72], wherein the first memory deck and the second memory deck both comprise a plurality of memory cell layers and a word line layer corresponding to each memory cell layer [para. 22-24], and at least one dummy memory cell layer [Fig. 10: 1017, 1021, 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the first memory deck and the second memory deck [see Fig. 10, interface dummy WLs are provided on an internal boundary of a deck, here on either side of poly plug 1051, para. 73]; and
a peripheral circuit [Fig. 1: 116] coupled to the memory cell array [see Fig. 1, para. 35] and configured to:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84], apply a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and apply a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
apply a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92]; and
apply a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84], and
a memory controller [Fig. 17: 1724] coupled to the one or more memory devices [Fig. 17: 1712] and configured to control the one or more memory devices [para. 100].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triqqered and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck. Fastow et al. disclose the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] is equal or greater than the first pass voltage [Fig. 13: Vpass_sel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61].
Chen et al. teach a 0 V, or another relatively low turn-off voltage applied to the dummy word lines (e.g., WLDL and WLDU in FIG. 5) [Fig. 11A: step 1104b, col. 21, lines 39-42 as well as col. 15, lines 6-8] that is lower than the nominal pass voltage Vpass (8-10V) can be applied to the remaining non-interface unselected word lines (e.g., WL0-WL46 and WL49-WL95) while a program operation is performed [see Fig. 5 and Fig. 11A, col. 5, lines 37-40 as well as col. 21, lines 34-35, 55-57] and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck [see Fig. 5, the voltages of the interface unselected word lines (e.g., WLDL and WLDU in FIG. 5) are kept at a turn-off voltage such as 0 V throughout the program phase to block the residue electrons in the lower tier (Fig. 5: 600) from reaching the upper tier (Fig. 5: 601), col. 5, lines 27-30].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chen et al. and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Chen et al. and greater than a threshold voltage below which hot electron injection is triqqered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to block the residue electrons in the second deck from reaching the first deck, advantageously avoids any delay in the programming time [see Chen et al.’s col. 5, lines 29-42] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding independent claim 12, Fastow et al. disclose an operation method of a memory device, comprising:
when performing a program operation on a selected memory cell layer in the first memory deck [see Fig. 13, para. 26 as well as para. 83-84] of a memory cell array [Fig. 10: 1000] of the memory device [Fig. 1: 100], applying a program voltage [Fig. 13: VPGM] to a word line layer corresponding to the selected memory cell layer [Fig. 16: step 1630, para. 93] and applying a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92];
applying a second pass voltage [Fig. 13: Vpass_unsel] to the word line layer corresponding to the plurality of memory cell layers in the second memory deck [Fig. 16: step 1620, para. 92] which is stacked with the first memory deck [see Fig. 10, para. 24 as well as para. 72]; and
applying a third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317] corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
the second pass voltage is less than the first pass voltage [the Vpass_unsel is smaller than Vpass_sel in order to enable multiple program/erase cycles in the selected deck without disturbing the unselected decks, para. 84].
However, Fastow et al. are silent with respect to the third pass voltage is less than the second pass voltage and greater than a threshold voltage below which hot electron injection is triqqered and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck. Fastow et al. disclose the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] is equal or greater than the first pass voltage [Fig. 13: Vpass_sel] to increase the potential in inhibited pillars (i.e., increased pillar boosting) [para. 61].
Chen et al. teach a 0 V, or another relatively low turn-off voltage applied to the dummy word lines (e.g., WLDL and WLDU in FIG. 5) [Fig. 11A: step 1104b, col. 21, lines 39-42 as well as col. 15, lines 6-8] that is lower than the nominal pass voltage Vpass (8-10V) can be applied to the remaining non-interface unselected word lines (e.g., WL0-WL46 and WL49-WL95) while a program operation is performed [see Fig. 5 and Fig. 11A, col. 5, lines 37-40 as well as col. 21, lines 34-35, 55-57] and applying the third pass voltage forms a soft cut voltage between a memory layer group of the first memory deck and a memory layer group of the second memory deck, the soft cut voltage forming a potential barrier for channel residual electrons that suppresses migration of the channel residual electrons from the second memory deck toward a channel region corresponding to the selected memory cell layer in the first memory deck [see Fig. 5, the voltages of the interface unselected word lines (e.g., WLDL and WLDU in FIG. 5) are kept at a turn-off voltage such as 0 V throughout the program phase to block the residue electrons in the lower tier (Fig. 5: 600) from reaching the upper tier (Fig. 5: 601), col. 5, lines 27-30].
Furthermore, Park 079 teaches the first disturbance prevention voltage Vd1 is a voltage that turns on the first dummy memory cell (DMC1) that is greater than a threshold voltage Vth of the first dummy memory cell (DMC1) to prevent a disturbance due to a hot carrier occurs [see Fig. 4, para. 47-49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chen et al. and Park 079 to the teaching of Fastow et al. such that applying a voltage to a dummy word line that is lower than a voltage applied to non-selected word line as taught by Chen et al. and greater than a threshold voltage below which hot electron injection is triqqered as taught by Park 079 into Fastow et al.’s dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck while a program operation is performed in order to block the residue electrons in the second deck from reaching the first deck, advantageously avoids any delay in the programming time [see Chen et al.’s col. 5, lines 29-42] and prevent a disturbance due to a hot carrier [see Park 079’s para. 47].
Regarding claim 13, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the applying a first pass voltage [Fig. 13: Vpass_sel] to a word line layer corresponding to an unselected memory cell layer in the first memory deck [Fig. 16: step 1620, para. 92] comprises:
applying the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 14, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein
the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 15, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 12.
Furthermore, Fastow et al. disclose wherein the at least one dummy word line layer at the junction position of the first memory deck and the second memory deck comprises a first dummy word line layer [Fig. 10: 1017] located in the first memory deck [Fig. 10: 1040] and a second dummy word line layer [Fig. 10: 1031] located in the second memory deck [Fig. 10: 1060, para. 72-73], and the third pass voltage comprises a third sub-pass voltage [Fig. 13: Vpass_int1] and a fourth sub-pass voltage [Fig. 13: Vpass_int2], wherein
the applying a third pass voltage to a dummy word line layer corresponding to at least one dummy memory cell layer at a junction position of the first memory deck and the second memory deck comprises:
applying the third sub-pass voltage [Fig. 13: Vpass_int1] to the first dummy word line layer [Fig. 13: 1317] and applying the fourth sub-pass voltage [Fig. 13: Vpass_int2] to the second dummy word line layer [Fig. 13: 1338], wherein the third sub-pass voltage is different from the fourth sub-pass voltage.
Regarding claim 17, Fastow et al. in combination with Chen et al. and Park 079 the limitations with respect to claim 14.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Regarding claim 18, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 11.
Furthermore, Fastow et al. disclose wherein the unselected memory cell layer in the first memory deck [Fig. 9: 910] comprises a memory cell layer in a programmed state [Fig. 9: 917] and a memory cell layer in an erased state [Fig. 9: 920, para. 68], and the first pass voltage comprises a first sub-pass voltage and a second sub-pass voltage, wherein
the peripheral circuit is configured to:
apply the first sub-pass voltage [Fig. 9: Vpassr] to a word line layer corresponding to the memory cell layer in the programmed state [a voltage Vpassr applied to the programmed WLs 917 of selected decks 913, para. 69]; and
apply the second sub-pass voltage [Fig. 9: Vpassr_low 2] to a word line layer corresponding to the memory cell layer in the erased state [a voltage Vpassr_low 2 applied to the erased WLs 920 of selected decks 913, para. 69], wherein
the first sub-pass voltage is different from the second sub-pass voltage [see Fig. 8, Vpassr > Vpassr_low2, para. 69].
Regarding claim 19, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 11.
Furthermore, Fastow et al. disclose wherein the memory cell array [Fig. 10: 1000] further comprises a third memory deck [Fig. 10: 1050] stacked with both the first memory deck [Fig. 10: 1040] and the second memory deck [Fig. 10: 1060, para. 72], wherein the third memory deck [Fig. 10: 1050] is stacked with the first memory deck [Fig. 10: 1040], at least one dummy memory cell layer [Fig. 10: 1017, 1021] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the first memory deck [para. 73], and the peripheral circuit [Fig. 1: 116] is configured to apply the third pass voltage [Fig. 13: Vpass_int1, Vpass_int2] to the dummy word line layer [Fig. 13: 1317, 1323] corresponding to the at least one dummy memory cell layer at the junction position between the first memory deck [Fig. 13: 1315] and the third memory deck [Fig. 13: 1325].
Regarding claim 20, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claim 11.
Furthermore, Fastow et al. disclose the third memory deck [Fig. 10: 1050] is provided adjacent to the second memory deck [Fig. 10: 1060], at least one dummy memory cell layer [Fig. 10: 1031] and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the third memory deck and the second memory deck [para. 73], and the peripheral circuit is configured to apply the second pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position between the second memory deck and the third memory deck [para. 139].
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 20190043591) in view of Chen et al. (US 10438671) and Park et al. (US 20110305079; hereinafter “Park 079”) as applied to claims 1 and 12 above, and further in view of Rajagiri et al. (US 20240028253).
Regarding claims 9 and 16, Fastow et al. in combination with Chen et al. and Park 079 teach the limitations with respect to claims 1 and 12.
However, Fastow et al. in combination with Chen et al. and Park 079 are silent with respect to the peripheral circuit is configured to:
when performing a program operation on the plurality of memory cell layers in the first memory deck, perform one of a sequential program operation or a reversed program operation on the plurality of memory cell layers in the first memory deck.
Rajagiri et al. teach a NAND string can be programmed from source-to-drain and in a drain-to-source configuration, i.e., both normal and reverse word line order [para. 56-57].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Rajagiri et al. to the teaching of Fastow et al. in combination with Chen et al. and Park 079 such that implementing the deck programming as taught by Fastow et al. in combination with Chen et al. and Park 079 to select either sequential or reversed program operation within the deck during program as taught by Rajagiri et al. to lower the lateral gradient and mitigate the hot-electron injection phenomenon [see Rajagiri et al.’s para. 17-19].
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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