DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/11/2026 has been entered.
Terminal Disclaimer
The terminal disclaimer filed on 06/11/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 11405035, U.S. Patent No. 11405031 and U.S. Patent No. 12542549 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 12, the recitation “in a first static state of the control signal in which the control signal is charged to the positive voltage, charging a gate terminal of the nMOS transistor and a gate terminal of the pMOS transistor to the positive voltage” on lines 7-9 is indefinite because it is misdescriptive since the disclosure discloses in Figures 2B and 3B (also see par. [0024] and [0028]) that in a first static state of the control signal (IN) is at the positive voltage (+V), both G1 and G2 are at 0V (i.e., G1 and G2 are not the positive voltage +V) as the claim recites “charging a gate terminal of the nMOS transistor and a gate terminal of the pMOS transistor to the positive voltage”. Further, the recitation “in a second static state of the control signal in which the control signal is charged to the negative voltage, charging the gate terminal of the nMOS transistor and the gate terminal of the pMOS transistor to the negative voltage” on lines 13-15 is also indefinite because it is misdescriptive since the disclosure discloses in Figures 2A and 3A (also see par. [0022] and [0028]) that in a second static state of the control signal (IN) is at the negative voltage (-V), both G1 and G2 are at 0V (i.e., G1 and G2 are not the negative voltage -V) as the claim recites “charging a gate terminal of the nMOS transistor and a gate terminal of the pMOS transistor to the negative voltage”. Clarification and/or appropriate correction is required.
Claims 13-15 are indefinite because they depend on claim 12.
Allowable Subject Matter
Claims 2, 3, 6-11 and 16-22 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowed because the closet prior art (Shanjani et al., US 2018/0167062 in Figures 4A-4C) of record teaches a FET switch stark (420) comprising a stacked arrangement of FET switches (M1-Mn), a gate resistor network (Rg1, Rg2…Rgn), a common gate resistor ((Rds1, Rds2…Rdsn); and a serial arrangement of an NMOS transistor and a pMOS transistor (nMOS 411 in series with pMOS 413, or nMOS 421 in series with pMOS 412) with the connections and operations as recited in the claim. However, the closet prior art (Shanjani et al., US 2018/0167062 in Figures 4A-4C) of record, taken alone or in combination, fails to teach or suggest a FET switch stack comprising the limitations “a pulse generator configured to pulse a first pulsed signal to a positive voltage in response to a transition of the voltage signal from a negative voltage to the positive voltage and to pulse a second pulsed signal to the negative voltage in response to a transition of the voltage signal from the positive voltage to the negative voltage; and wherein a gate of the nMOS transistor is coupled to a node for the first pulsed signal, and a gate of the pMOS transistor is coupled to a node for the second pulsed signal” in combination with other limitations, as a whole, as recited in the claim.
Claims 6-11 are allowed because they depend on claim 2.
Claim 16 is allowed because the closet prior art (Shanjani et al., US 2018/0167062 in Figures 4A-4C) of record teaches a FET switch stark (420) comprising a stacked arrangement of FET switches (M1-Mn), a gate resistor network (Rg1, Rg2…Rgn), a common gate resistor ((Rds1, Rds2…Rdsn); and a serial arrangement of an NMOS transistor and a pMOS transistor (nMOS 411 in series with pMOS 413, or nMOS 421 in series with pMOS 412) with the connections and operations as recited in the claim. However, the closet prior art (Shanjani et al., US 2018/0167062 in Figures 4A-4C) of record, taken alone or in combination, fails to teach or suggest a FET switch stack comprising the limitations “a clamping circuit coupled across the pMOS transistor, the clamping circuit configured to provide a current conduction path upon a decrease of a gate voltage of the pMOS transistor” in combination with other limitations, as a whole, as recited in the claim.
Claims 17-22 are allowed because they depend on claim 16.
Response to Arguments
Applicant’s arguments filed on 06/11/26 have been considered but are moot in view of the new ground of rejection(s).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights