DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,405,035 (the ‘035 patent, hereafter). Although the claims at issue are not identical, they are not patentably distinct from each other because they are drawn to substantially the same embodiment of the invention. In particularly, claims 1-20 of the ‘035 patent teaches a FET switch stack, and a method thereof, that comprises a stacked arrangement of FET switches, a gate resistor network comprising resistors to gate terminals of the FET switches, and one or more common gate resistors, and a common gate resistor bypass arrangement comprising at least one series combination of an nMOS transistor and a pMOS transistor connected across the one or more common gate resistors with the connections and operations as recited in claims 2-20 of the instant application. Note that the functions “i) bypass” and “ii) not to bypass” (as recited in the last 13 lines of claim 1 of the ‘035 patent) are obviously can be generated by “a pulse generator”; and claims 5-8 and of the ‘035 patent further recites “control circuitry” which is equivalent to “a pulse generator”.
Claims 2-20 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-31 of U.S. Patent No. 11,405,031 (the ‘031 patent, hereafter). Although the claims at issue are not identical, they are not patentably distinct from each other because they are drawn to substantially the same embodiment of the invention. In particularly, claims 1-31 of the ‘031 patent teaches a FET switch stack, and a method thereof, that comprises a stacked arrangement of FET switches, a gate resistor network comprising resistors to gate terminals of the FET switches, and one or more common gate resistors, and a common gate resistor bypass arrangement comprising at least one series combination of an nMOS transistor and a pMOS transistor connected across the one or more common gate resistors with the connections and operations as recited in claims 2-20 of the instant application. Note that the functions “i) bypass” and “ii) not to bypass” (as recited in the last 14 lines of claim 1 of the ‘031 patent) are obviously can be generated by “a pulse generator”; and claims 7-10 and 14-21 of the ‘031 patent further “a pulse generator”.
Claims 12-15 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,542,549 (of the copending Application No. 18/427,598 in previously office action), (the ‘549 patent, hereafter). Although the claims at issue are not identical, they are not patentably distinct from each other because they are drawn to substantially the same embodiment of the invention. In particularly, claims 1-24 of the ‘549 patent teaches a method to control bypass a resistor across a series combination of an nMOS transistor and a pMOS transistor to control switching an RF FET switch comprising the steps that teaches the limitations of claims 12-15 of the instant application (note that it is obvious for the ‘549 patent to implement in the “SOI process”).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the FET switch stack comprising “a stacked arrangement of FET switches, a gate resistor” (in addition to a common gate resistor and a pulse generator) as recited in the claims must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shanjani et al. (US 2018/0167062).
For claim 16, Figures 4A, 4A’, 4B, and 4C of Shanjani et al. each teaches a FET switch stack (420) comprising: a stacked arrangement of FET switches (M1-Mn); a gate resistor network (Rg1, Rg2, … Rgn) coupled to a gate of each of the FET switches(M1-Mn) in the stacked arrangement of FET switches (420); a common gate resistor (Rds1-Rds2) coupled between a node for a voltage signal (input of 401) and the gate resistor network (Rg1, Rg2, … Rgn); and a serial arrangement of an nMOS transistor and a pMOS transistor (NMOS 411 series with PMOS 413, or NMOS 421 series with PMOS 412) coupled in parallel with the common gate resistor (Rds1, Rds2)
For claims 17-18, Figures 4A, 4B, and 4C of Shanjani et al. further teaches: a pulse generator (401, Filter cap, Rg11, Rg12, Rg21, Rg22) configured to pulse on the nMOS transistor (NMOS 411 or NMOS 421) in response to a transition of the voltage signal (input of 401) from a first voltage (Vg low) to a second voltage (Vg high) that is greater than the first voltage; wherein the first voltage is a negative voltage and the second voltage is a positive voltage (Vg is from -V to +V, see [0050] and [0059]).
For claims 19-20, Figures 4A, 4B, and 4C of Shanjani et al. further teaches: a pulse generator (401, Filter cap, Rg11, Rg12, Rg21, Rg22) configured to pulse on the pMOS transistor (PMOS 412 or PMOS 413) in response to a transition of the voltage signal (input of 401) from a first voltage (Vg high) to a second voltage (Vg low) that is less than the first voltage; wherein the first voltage is a positive voltage and the second voltage is a negative voltage (Vg is +V to -V, see [0050] and [0059]).
Allowable Subject Matter
Claims 2-15 would be allowed if filing a proper Terminal Disclaimer.
Response to Arguments
Applicant's arguments filed on 12/11/25 for newly added claims 16-20 have been fully considered but they are not persuasive.
Applicant argues that “new claims 16-20 are supported as discussed analogously with regard to claim 2”, but does not specifically what the reference fails to teach for claims 16-20. Hence, claims 16-20 are rejected for the reasons set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-8101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842