Prosecution Insights
Last updated: July 17, 2026
Application No. 18/409,221

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jan 10, 2024
Priority
May 03, 2023 — RE 10-2023-0057807
Examiner
HOSSAIN, MOAZZAM
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
725 granted / 825 resolved
+19.9% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
47 currently pending
Career history
862
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
70.3%
+30.3% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 825 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election, with traverse, of Species I of which claims read upon 1-10 in “Response to Election / Restriction Filed - 06/05/2026”, is acknowledged. This office action considers claims 1-20 pending for prosecution, of which, non-elected claims 11-20 are withdrawn, and elected claims 1-10 are examined on their merits. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 150; Fig 7; [0052]) = (element 150; Figure No. 7; Paragraph No. [0052]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference, in this case Chen, citation may not be preceded by the inventor tag, wherein the other reference citation, for example Wang and like, will carry inventor tag. These conventions are used throughout this document. Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Tzu Pei et al. (US 20230395504 A1) hereinafter Chen, in view of WANG; Shih-Wei. (US 20180286959 A1) hereinafter Wang. Regarding Claim 1. Chen teaches a semiconductor device (40; first cited [0024]) comprising: (see the entire document, Figs 3,7,19-20, along with other figs 1 to 6 and referenced subject matter for details, specifically [0054+], and as cited below): PNG media_image1.png 367 956 media_image1.png Greyscale Chen Figure 6 -> Figure 71 a mold layer (comprising {76,110 /78} [0037] labelled as dielectric layer in [0037] which is synonymous of mold as mold materials are defined in instant specification [0014]: mold layer 210 includes at least one of insulating materials, for example, one of oxide materials or nitride materials) defining a trench (where 150,74 is formed; Fig 7; trench (cavity) 140 in Fig 6; [0049]); and a conductive structure ({150,74}; Fig 7; [0052]) disposed on the trench, wherein the conductive structure comprises a conductive layer ({150,74}) comprising upper (150) and lower portions (74) and a liner (75) comprising a base portion (flat bottom of 75) and a sidewall portion (sidewall of 75) on the base portion (flat bottom of 75), wherein the upper portion (150) of the conductive layer is disposed at a level higher (depicted in Fig 7) than the sidewall portion (sidewall of 75) of the liner, wherein the sidewall portion (sidewall of 75) of the liner (75) is interposed between the lower portion (sidewall of 75) of the conductive layer (75) and the mold layer ((comprising {76,110 /78} [0037]) a top surface of the base portion (flat bottom of 75) of the liner ( 75) is in contact with a bottom surface of the lower portion (74) of the conductive layer, and but, Chen does not expressly “a width of the sidewall portion (sidewall of 75) of the liner (75) decreases as a vertical level of the liner ( 75) increases (vertically up)”. The difference between Chen and the claim 1 is the width of the sidewall portion (sidewall of 75) of the liner ( 75) does not decreases as a vertical level of the liner ( 75) increases. However, in the analogous art, Wang teaches, in figures 19-22, [0029]), a liner layer 281, wherein width of the sidewall portion (281S->281) of the liner ( 281) decreases (fig depicted in figs 20-22) as a vertical level of the liner ( 281) increases (vertically up) . PNG media_image2.png 378 986 media_image2.png Greyscale Wang Figure 20 -> Figure 22 Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen liner witdh in view of Wang’s 281, and thereafter, the combination of (Chen and Wang)’s semiconductor device comprises the width of the sidewall portion (sidewall of 75 in view of Wang ) of the liner (75) decreases as a vertical level of the liner ( 75) increases (vertically up), since this modification, at least, increases conducting area of lower portion 74 at contact points of upper portion 150 to have symmetric current flow. Regarding Claim 2. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, wherein the conductive layer and the liner comprise molybdenum (molybdenum; [0068,0094]), and the liner further comprises oxygen (O; [0041]). Regarding Claim 3. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, wherein the conductive layer comprises molybdenum (Mo; (molybdenum; [0068,0094])), and the liner comprises titanium nitride (TiN; [0018,0039 0067]: Titanium Nitride). Regarding Claim 5. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, further comprising a substrate (50; Fig 3; [0026] containing silicon (Si)( siliconl [0027]), wherein the mold layer {76,110 /78} and the conductive structure ({150,74}) are provided on the substrate. Regarding Claim 6. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, further comprising a material layer (54; Figs 3/6; [0039]) enclosed by the mold layer {76,110 /78};[0037]), wherein the conductive structure ({150,74}) is provided on the material layer (54), and a width of a top surface of the material layer (54; Fig 3/6) is equal to a width of a bottom surface of the conductive structure {74). Regarding Claim 7. the combination of (Chen and Wang) as applied to the semiconductor device of claim 6, further teaches, wherein the material layer comprises a metallic material (doped portion [0039]) . Regarding Claim 8. the combination of (Chen and Wang) as applied to the semiconductor device of claim 6, further teaches, wherein the material layer comprises silicon (Si) ([0039]: 54 is silicon). Regarding Claim 9. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, wherein a width (W1; Fig 20; [0109]) of a bottom surface of the conductive structure is equal to or less than 20 nm ([0109]). Regarding Claim 10. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, further teaches, wherein a height of the conductive structure ({150c, 74c}; Fig 19-20; [0106]) ranges from 100 nm to 1000 nm. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen; Tzu Pei et al. (US 20230395504 A1) hereinafter Chen, in view of WANG; Shih-Wei. (US 20180286959 A1) hereinafter Wang; and in further view of KITAMURA; Masayuki et al, (US 20210265266 A1) hereinafter Kitamura Regarding Claim 4. the combination of (Chen and Wang) as applied to the semiconductor device of claim 1, does not expressly disclose , wherein the conductive layer ({150,74}; Fig 7; [0052]) and the liner (75; Fig 7) comprise chlorine (Cl), and a chlorine concentration of the conductive layer is higher than a chlorine concentration of the liner. However, in the analogous art, Kitamura teaches, in (Fig 6; [0028,0030, 0040,0060]), chlorine deposited along with Ti to form trench (via) 6 and barrier layer 6a, [0038]), wherein [0039] The chlorine treatment can adjust the chlorine concentration in the barrier metal layer 6a to be not more than 5.0×10.sup.21 atoms/cm.sup.3 (or to be less than or equal to 5.0×10.sup.21 atoms/cm.sup.3). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of (Chen and Wang) in view of Kitamura teaching, and thereafter, the combination of (Chen, Wang and Kitamura)’s semiconductor device comprises wherein the conductive layer ({150,74}; Fig 7; [0052]) and the liner (75; Fig 7) comprise chlorine (Cl), and a chlorine concentration of the conductive layer is higher than a chlorine concentration of the liner since this modification, at least, improves metal interconnect properties from deteriorating due to the influence of the via plug (Kitamura [0003]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898 June 18, 2026
Read full office action

Prosecution Timeline

Jan 10, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 825 resolved cases by this examiner. Grant probability derived from career allowance rate.

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