Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 13 and 17
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 1/10/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 2 is objected to because of the following informalities: line: 3 recites “including the NAND”. Examiner suggests “string” be added after “NAND”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Independent claim 1 recites: “bit line select switches” in line: 6;
Followed by: “the bit line switches” in line: 7; are they referring to same switch?
It further recites: “bit line pre-charge circuit” in line: 8;
Followed by: “the bit lines pre-charge circuit in line: 10; are they referring to same circuit?
All the dependent claims 2-12 carry the same deficit and henceforth are rejected.
Claim 16 recites “determining whether to perform a selected word line”. Metes and bounds of claim 16 is unclear.
Independent claim 17 recites: “connectable” in line: 5 and 6. It requires clarification whether the circuit is configured to connect with some lines through switches.
Independent claim 17 recites: “channel pre-charge the block of NAND stings” in line: 11 and
“subsequent to channel pre-charging the block of NAND strings” in line: 15. The phrase doesn’t carry any meaningful limitation.
All the dependent claims 18-20 carry the same deficit and henceforth are rejected.
Claim 18 further recites: “prior to channel pre-charging the block of NAND strings” in line: 3.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Applicant is requested to correct all the claim phrases as appropriate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 13-14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20050117399) in view of Lim et al. (US 9478261).
Regarding independent claim 13, Kwon discloses a method (Figs. 3-11), comprising;
performing a first programming operation on a block of non-volatile memory (110; Fig. 4 and [0048]) comprising a plurality of NAND strings (111; Fig. 4 and [0048]), comprising:
pre-charging the plurality of the NAND strings (Fig. 3) by:
biasing the plurality of NAND strings at a program inhibit level (step S140 of Fig. 3 and [0045]) from a corresponding bit line by a bit line pre-charge circuit through one or more bit line bias switches (Fig. 4 shows Y-Gate connects to corresponding bit line); and
subsequently discharging selected ones of the plurality NAND strings through the corresponding bit line and a corresponding bit line select switch to a corresponding one of a plurality of sense amplifier circuits (Fig. 5 and [0055] describes that boosted voltage of the channel region of the cell string becomes discharged through the bit line to a corresponding sense amplification and latch unit 140-0-140_n. Otherwise, the discharging may occur responsive to activation of the NMOS transistor MN2), the bit line pre-charge circuit being separate from the sense amplifier circuits (Fig. 4 shows Y-Gate different than sense amplifiers 140_i);
subsequent to pre-charging the plurality of the NAND strings, applying a first programming pulse to a first selected word line along which the plurality of NAND strings are connected (Fig. 5 shows applying voltage pulse Vpgm to selected word line after pre-charging); and
Kwon does not disclose subsequent to applying the first programming pulse, program verifying the selected ones of the plurality of NAND strings by:
charging an internal node of the corresponding sense amplifier; and
discharging the internal node through the selected one of the plurality of NAND string at a rate dependent on a threshold voltage of a memory cell of the selected NAND string connected along the first selected word line.
However, Lim teaches subsequent to applying the first programming pulse, program verifying the selected ones of the plurality of NAND strings ((67) describes that although an example of the read operation is described in an embodiment of the present disclosure, the embodiment may be identically applied to a sensing operation of the page buffer during an operation for sensing the threshold voltage of the memory cell, for example, the program verification operation) by:
charging an internal node of the corresponding sense amplifier (Figs. 3-5 and (54) shows internal node CSO and describes that each of the plurality of page buffers PB1 to PBm pre-charge the internal node CSO to a certain potential level); and
discharging the internal node through the selected one of the plurality of NAND string at a rate dependent on a threshold voltage of a memory cell of the selected NAND string connected along the first selected word line (Figs. 3-5 and (34) and (40) describes that internal node discharge circuit 134 may be connected between the internal node CSO and a ground voltage Vss, and may discharge the internal node CSO to a low level. Also, (22), (59) and (62) describes that discharging depends on the threshold voltage of the memory cell).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lim to Kwon in order to improve accuracy of the program verification operation and a threshold voltage distribution of the memory cell during the program operation as taught by Lim ((67)).
Regarding claim 14, Kwon and Lim together disclose all the elements of claim 13 as above and through Kwon further discharging the selected ones of the plurality NAND strings through the corresponding bit line and the corresponding bit line select switch to the corresponding one of the plurality of sense amplifier circuits (Fig. 5 and [0055] describes that boosted voltage of the channel region of the cell string becomes discharged through the bit line to a corresponding sense amplification and latch unit 140-0-140_n. Otherwise, the discharging may occur responsive to activation of the NMOS transistor MN2) comprises:
biasing the corresponding bit line select switches such that a voltage applied to transistors of the corresponding sense amplifier circuit does not exceed a maximum operating voltage for the transistors (Here examiner asserts that this is known principle of operation that the device won’t exceed maximum operating voltage).
Claim 4 is written in product form of corresponding method claim 14 and henceforth rejected the same way.
Independent claim 17 is written in system level of corresponding method claim 13 and henceforth rejected the same way.
Claims 1, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20050117399) in view of Lim et al. (US 9478261) and Hu (US 10354737).
Regarding claim 15, Kwon and Lim together disclose all the elements of claim 13 as above and through Kwon further performing a second programming operation (Here examiner asserts that second programming operation could be well-known looping during programming) on the block of non-volatile memory (Figs. 3-4), comprising:
pre-charging the plurality of the NAND strings (Fig. 3) by:
biasing the plurality of NAND strings at the program inhibit level from a source line; and
subsequently discharging selected ones of the plurality NAND strings through a corresponding bit line and a corresponding bit line select switch to a corresponding one of a plurality of sense amplifier circuits (Fig. 5 and [0055] describes that boosted voltage of the channel region of the cell string becomes discharged through the bit line to a corresponding sense amplification and latch unit 140-0-140_n. Otherwise, the discharging may occur responsive to activation of the NMOS transistor MN2), the bit line pre- charge circuit being separate from the sense amplifier circuits (Fig. 4 shows Y-Gate different than sense amplifiers 140_i);
applying a second programming pulse to a second selected word line along which the plurality of NAND strings are connected (Fig. 5 shows applying voltage pulse Vpgm to selected word line after pre-charging); and
Lim teaches subsequent to applying the first programming pulse, program verifying the selected ones of the plurality of NAND strings ((67) describes that although an example of the read operation is described in an embodiment of the present disclosure, the embodiment may be identically applied to a sensing operation of the page buffer during an operation for sensing the threshold voltage of the memory cell, for example, the program verification operation) by:
charging an internal node of the corresponding sense amplifier (Figs. 3-5 and (54) shows internal node CSO and describes that each of the plurality of page buffers PB1 to PBm pre-charge the internal node CSO to a certain potential level); and
discharging the internal node through the selected one of the plurality of NAND string at a rate dependent on a threshold voltage of a memory cell of the selected NAND string connected along the second selected word line (Figs. 3-5 and (34) and (40) describes that internal node discharge circuit 134 may be connected between the internal node CSO and a ground voltage Vss, and may discharge the internal node CSO to a low level. Also, (22), (59) and (62) describes that discharging depends on the threshold voltage of the memory cell).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lim to modified Kwon in order to improve accuracy of the program verification operation and a threshold voltage distribution of the memory cell during the program operation as taught by Lim ((67)),
Neither Kwon nor Lim disclose biasing the plurality of NAND strings at the program inhibit level from a source line;
However, Hu teaches biasing the plurality of NAND strings at the program inhibit level from a source line (claim 13 recites when programming the first set of memory cells, the control circuits are configured to pre-charge NAND strings to which the second set of memory cells belong from the source line to one of either a program inhibit voltage level or a program enable voltage level);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hu to modified Kwon in order to provide with schemes for the management of erase disturb in non-volatile memory systems that allow sub-block level erase as taught by Hu ((25)).
Independent claim 1 is written in product form of corresponding method claims 13 and 15 and henceforth rejected the same way.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 7/23/2025
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