Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species II in the reply filed on 06/07/2026 is acknowledged. Examiner notes that claim 10 was accidentally excluded for group I and will be examined with group I, Applicant states that claims 1-20 read on Species II however claim 4 requires “the upper surface of the via has a shape that is convex toward the wiring line” however this is only disclosed with respect to Species III Fig. 6C and not with respect to Species II Fig. 6B.
Claims 4 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/17/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICES WITH WIRING LINE ADHESION LAYER AND METHODS OF FABRICATING THE SAME.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Chen et. Al. (US 20210057273 A1 hereinafter Chen).
Regarding claim 1, Chen teaches in Figs. 2 and 9A or 9C, referring to Figs. 2 and 9A unless otherwise specified, with associated text a semiconductor device, comprising: a substrate 22 that includes an active pattern (area under channel, source and drain Fig. 2, [0019]); a channel pattern ([0019]) on the active pattern; a source/drain pattern ([0019]) electrically connected to the channel pattern ([0119]); a gate electrode on the channel pattern ([0019]); an interlayer dielectric (210, 212, 220 an d 222) layer on the gate electrode, wherein the interlayer dielectric layer includes a recess (224, 226 and opening filled with 2000) (Fig. 2, [0024] and [0026]); a via 2000 in the recess of the interlayer dielectric layer (Fig. 2, [0024]); a wiring line (234 and 236) on the interlayer dielectric layer and electrically connected to the via (Fig. 9A, [0033]); and an adhesion layer 232 between the wiring line and an upper surface of the interlayer dielectric layer (Fig. 9A, [0029] and [0031]), wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction (Fig. 9A), wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess (Fig. 9A).
Regarding claim 2, Chen teaches the wiring line includes a line portion (portion in trench 226) and a protrusion portion (portion in 224) that extends from the line portion in the first direction (Figs. 2 and 9A, [0033]), wherein the line portion is on the upper surface of the interlayer dielectric layer (Fig. 9A), and wherein at least a portion of the protrusion portion is in the recess of the interlayer dielectric layer (Fig. 9A).
Regarding claim 3, Chen teaches the protrusion portion of the wiring tine is in contact with the upper surface of the via (Fig. 9A).
Regarding claim 4, Chen teaches the upper surface of the via has a shape that is convex toward the wiring line (here the via is interpreted to be 242 of Fig. 9C).
Regarding claim 5, Chen teaches at least a portion of the upper surface of the via is exposed through the adhesion layer to be in contact with the wiring line (Fig. 9A, [0033]).
Regarding claim 6, Chen teaches the adhesion layer has a sidewall aligned with one sidewall of the wiring line (Fig. 9a).
Regarding claim 7, Chen teaches the via is electrically connected to the source/drain pattern or the gate electrode ([0024]).
Regarding claim 8, Chen teaches the wiring tine includes ruthenium (Ru) ([0033]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 and further in view of Min (US 20220223526 A1 hereinafter Min).
Regarding claim 9, Chen teaches the semiconductor device of claim 1, further comprising a contact (MEOL device-level contacts, such as gate contacts electrically coupled to gate structures and source/drain contacts electrically coupled to the epitaxial source/drain features [0033]) between the source/drain pattern and the via or between the gate electrode and the via ([0033]).
Chen does not specify the contact includes: a conductive pattern; and a barrier pattern on sidewalls and a lower surface of the conductive pattern
Min discloses in Fig. 32 with associated text a contact (170 or 180) similar to that of Chen that includes: a conductive pattern (170b or 180b); and a barrier pattern (170a or 180a) on sidewalls and a lower surface of the conductive pattern (Fig. 32, [0108] or [0114])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use contacts similar to those of Min for the contacts Chen because according to Min such structures are suitable for source drain contacts [0108] or gate contacts [0114] and so would be suitable for the contacts of Chen. It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chen and Min, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use the contacts of Min for those of Chen with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007). .
Regarding claim 10, Chen teaches the semiconductor device of claim 1.
Chen does not specify the channel pattern includes a plurality of semiconductor patterns that are spaced apart from each other and are stacked in the first direction, wherein the gate electrode includes: a plurality of inner electrodes between adjacent ones of the plurality of semiconductor patterns; and an outer electrode on an uppermost one of the plurality of semiconductor patterns.
Min discloses in Fig. 32 with associated text a channel pattern includes a plurality of semiconductor patterns UP1 that are spaced apart from each other and are stacked in the first direction (Fig. 32, [0221]-[0222]), wherein a gate electrode GS includes: a plurality of inner electrodes (GS between adjacent patterns UP1) between adjacent ones of the plurality of semiconductor patterns; and an outer electrode (GS between adjacent patterns UP1) on an uppermost one of the plurality of semiconductor patterns (Fig. 32, [0115] and [0224]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use contacts similar to those of Min for the contacts Chen because according to Min the sheet pattern UP1 may be connected to the first source/drain pattern 150. The sheet pattern UP1 may be a channel pattern used as a channel region of a transistor rand so would be suitable for forming the channel of Chen. It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chen and Min, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use the channel of Min for that of Chen with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007). .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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