Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 06/18/2026 is acknowledged.
Claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/18/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “THREE-DIMENSIONAL FIELD EFFECT TRANSISTOR HAVING INNER SIDEWALL SPACER”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Yang et. Al. (US 20190157444 A1 hereinafter Yang).
Regarding claim 1, Yang teaches in Figs. 22-28 with associated text a semiconductor device comprising: a substrate (100-105) including an active pattern 105; a channel pattern 124 on the active pattern (Fig. 24, [0023]), wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other (Fig. 24, [0024]); a source/drain pattern 240 electrically connected to the plurality of semiconductor patterns (Fig. 24, [0025]); a gate electrode 300 that extends in a first direction (2nd DIRECTION) on the channel pattern (Fig. 22, [0028]), wherein the gate electrode includes an inner gate electrode that is between first and second semiconductor patterns among the plurality of semiconductor patterns (Fig. 24, [0029]); and an inner gate spacer 210 between the inner gate electrode and the source/drain pattern , wherein the inner gate spacer includes a center portion (see annotated Fig. below) and an edge portion (see annotated Fig. below) that is adjacent to a first side of the center portion in the first direction, wherein the center portion has a first thickness in a second direction (1st DIRECTION), wherein the edge portion has a second thickness in the second direction, wherein the first thickness is greater than the second thickness (see annotated Fig. below or [0038], lines 9-12), wherein the first and second semiconductor patterns are adjacent to each other in a third direction (3rd DIRECTION) (Fig. 24), wherein the first direction is parallel with an upper surface of the substrate (Fig. 24), wherein the second direction is parallel with the upper surface of the substrate and intersects with the first direction, and wherein the third direction is perpendicular to the upper surface of the substrate (Figs 22-25).
PNG
media_image1.png
646
500
media_image1.png
Greyscale
Regarding claim 3, Yang teaches a thickness of the inner gate spacer in the second direction decreases from the center portion to the edge portion (Fig. 23).
Regarding claim 4, Yang teaches a high-k dielectric layer 280 between the inner gate spacer and the inner gate electrode (Fig. 22, [0029]).
Regarding claim 5, Yang teaches the inner gate spacer includes a first sidewall that is convex toward the inner gate electrode (Fig. 23).
Regarding claim 6, Yang teaches the inner gate spacer includes a second sidewall that is in contact with the source/drain pattern and is recessed toward the inner gate electrode (Figs. 22 and 24).
Regarding claim 7, Yang teaches a curvature of the first sidewall is greater than a curvature of the second sidewall (Fig. 23).
Regarding claim 8, Yang teaches the inner gate electrode includes a concave sidewall that is on the inner gate spacer (Fig. 23).
Regarding claim 16, Yang teaches a semiconductor device comprising: a substrate (100-105) including an active region 105; an active pattern 124 on the active region (Fig. 24, [0023]); a device isolation layer 130 adjacent to the active pattern (Fig. 28, [0017]); a channel pattern 124 and a source/drain pattern 240 on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns that are spaced apart from each other and stacked in a second direction (3rd DIRECTION), and wherein the source/drain pattern 240 is electrically connected to the plurality of semiconductor patterns (Fig. 24, [0024]); a gate electrode 310 that extends in a first direction (2nd DIRECTION) on the channel pattern, wherein the gate electrode includes an inner gate electrode that is between first and second semiconductor patterns among the plurality of semiconductor patterns (Fig. 24, [0029]); a gate insulating layer (280 and 210) between the first and second semiconductor patterns and the inner gate electrode (Fig. 24, [0028]), wherein the gate insulating layer includes an inner gate spacer 210 between the inner gate electrode and the source/drain pattern (Fig. 24, [0029]); an inner high-k dielectric layer between the inner gate electrode and the inner gate spacer; and a gate spacer on a sidewall of the gate electrode (Fig. 24, [0030]), wherein the first and second semiconductor patterns are adjacent to each other in the second direction (3rd DIRECTION), wherein the inner gate spacer includes a first edge portion, a second edge portion spaced apart from the first edge portion in the first direction, and a center portion between the first edge portion and the second edge portion, wherein a thickness of the inner gate spacer in a third direction (2nd DIRECTION) increases from the first edge portion toward the center portion (see annotated Fig. above), reaches a maximum value at the center portion (see annotated Fig. above), and decreases toward the second edge portion from the center portion (see annotated Fig. above), wherein the second direction is perpendicular to an upper surface of the substrate, wherein the first direction is parallel with the upper surface of the substrate, and wherein the third direction is parallel with the upper surface of the substrate and intersects with the first direction (Fig. 22-28).
Regarding claim 17, Yang teaches the inner gate spacer includes a first sidewall that is convex toward the inner gate electrode (Fig. 23).
Regarding claim 18, Yang teaches the inner gate spacer further includes a second sidewall that is in contact with the source/drain pattern wherein the second sidewall is recessed toward the inner gate electrode, and wherein a curvature of the first sidewall is greater than a curvature of the second sidewall (Fig. 23).
Regarding claim 19, Yang teaches the inner gate electrode includes a concave sidewall that is in contact with the inner high-k dielectric layer (Fig. 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Regarding claim 2, Yang teaches the semiconductor device of claim 1.
Yang does not specify a ratio of the second thickness to the first thickness is 0.2 to 0.8 however Yang depicts in Fig 23 with associated text the ratio of the second thickness to the first thickness being about 0.8 and so envisions a ratio of the second thickness to the first thickness is 0.2 to 0.8 and teaches generally that thickness ratios of the spacer may be varied.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to a ratio of the second thickness to the first thickness is 0.2 to 0.8 with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as applied to claims 1 and 16 and further in view of Cheng et. Al. (US 20190148515 A1 hereinafter Cheng).
Regarding claims 9 and 20, Yang teaches the semiconductor device of claim 1 or 16.
Yang does not specify the inner gate spacer includes a first outer wall that is in contact with the source/drain pattern and convex toward the source/drain pattern, and a second outer wall that is on the inner gate electrode or inner high-k dielectric and recessed toward the source/drain pattern.
Cheng discloses in Figs. 3A with associated text a device similar to that of Yang wherein an inner gate spacer 65 includes a first outer wall that is in contact with a source/drain pattern 55 and convex toward the source/drain pattern (Fig. 3A [0039]), and a second outer wall that is on the inner gate electrode 84 and the inner high-k dielectric 82 and recessed toward the source/drain pattern (Fig. 3A, [0039])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use spacers with a shape at least in the z direction similar to those of Cheng in the device of Yang because according to Cheng the inner spacer 65 has a cross sectional shape along the X direction formed in a recess formed in the source/drain region and not in the channel region ([0040]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shin et. Al. (US 20220165729 A1) teaches a device in Fig. 2C having a spacer GSv relevant to claims 9 and 20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AARON J GRAY/Examiner, Art Unit 2897
Prosecution Insights