Prosecution Insights
Last updated: April 19, 2026
Application No. 18/409,545

MULTI-TRAINED SCALABLE PREFETCHER, AND RELATED METHODS

Final Rejection §102
Filed
Jan 10, 2024
Examiner
YU, JAE UN
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Ampere Computing LLC
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
666 granted / 741 resolved
+34.9% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
9 currently pending
Career history
750
Total Applications
across all art units

Statute-Specific Performance

§101
4.9%
-35.1% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 741 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 2, 3, 11-13, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kapil et al. (US 2015/0339233), “Kapil”. 2. As per claim 1, Kapil discloses a prefetcher configured to: receive a first memory address of requested data [a base address, abstract]; generate a first plurality of address offsets [a plurality of offsets, abstract]; and generate a first plurality of prefetch requests directed to one or more prefetch addresses [“prefetching operations”, abstract], each of the one or more prefetch addresses based on the first memory address [a base address, abstract] and a corresponding one of the first plurality of address offsets [a plurality of offsets, abstract]. 3. As per claim 2, Kapil discloses the prefetcher further configured to: receive an activity level indicator indicating an activity level of a data interface; and based on the activity level indicator, provide a second plurality of prefetch requests among the first plurality of prefetch requests to a prefetch request buffer [vector-indirect prefetch based on scatter/gather type memory operations, paragraph 5]. 4. As per claim 3, Kapil discloses to determine the second plurality of prefetch requests based on priority levels corresponding to each of the first plurality of address offsets [vector-indirect prefetch based on scatter/gather type memory operations, paragraph 5]. 5. As per claims 11-13 and 21, the examiner direct the applicant’s attention to claims rejection above. Arguments Concerning Prior Art Rejection Regarding claim 1, the applicant argues that the cited prior art teaches receiving prefetch instructions and associated offsets instead of claimed generation of prefetch requests and associated address offsets (emphasis added). However, the system of the cited prior art receives prefetch instructions, which means that such prefetch instructions necessarily have been generated prior to the receiving operation. Thus, the rejection is proper. Regarding claim 2, the applicant argues that the cited prior art does not disclose “an activity level of a data interface” used for prefetch operation(s). However, as the applicant acknowledges, Kapil discloses in paragraph 5, scatter/gather type memory operations used for vector-indirect prefetch. Such scatter/gather type memory operations are interpreted as the claimed “activity level of a data interface”. Regarding claim 3, the examiner interprets the “priority levels” of claim 3 as the “activity level” of claim 2, and therefore rejected for the same reason(s). The examiner suggests the applicant to further define in the claim language what these “priority levels” and “activity level” really are. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. A. Allowable Subject Matter Claims 4-10 and 14-20 are objected to. The closest prior art of record, “Kapil” discloses an offset based prefetch in the abstract. The primary reasons for allowance of claims 4 and 14 in the instant application is the combination with the inclusion in these claims that “a plurality of offset generators configured to generate the first plurality of address offsets, wherein each of the plurality of offset generators employs one of a plurality of algorithms each distinct from the others”. The prior art of record neither anticipates nor renders obvious the above recited combination. As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP. B. Claims Rejected Claims 1-3, 11-13, and 21 are rejected. C. Direction for Future Remarks Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAE U YU/Primary Examiner, Art Unit 2138
Read full office action

Prosecution Timeline

Jan 10, 2024
Application Filed
Sep 11, 2025
Non-Final Rejection — §102
Dec 09, 2025
Examiner Interview Summary
Dec 09, 2025
Applicant Interview (Telephonic)
Dec 31, 2025
Response Filed
Mar 18, 2026
Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+10.3%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 741 resolved cases by this examiner. Grant probability derived from career allow rate.

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