Prosecution Insights
Last updated: July 17, 2026
Application No. 18/409,702

MICROELECTRONIC DEVICES INCLUDING THROUGH-SILICON VIAS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS

Non-Final OA §112
Filed
Jan 10, 2024
Priority
Feb 23, 2023 — provisional 63/486,543
Examiner
HOQUE, MOHAMMAD M
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
627 granted / 737 resolved
+17.1% vs TC avg
Moderate +9% lift
Without
With
+9.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
43 currently pending
Career history
777
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
86.4%
+46.4% vs TC avg
§102
8.0%
-32.0% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 737 resolved cases

Office Action

§112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of species C/fig. 4-5, reflected in claims 1-8, 10-13 and 16-18 in the reply filed on 05/04/2026 is acknowledged. Claims 9, 14-15 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group. Claims 19-20 are cancelled. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 13 and 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 13 recites “a memory array structure bonded to a first side of the control circuitry structure and comprising an array of memory cells; a bond pad overlying a second side of the control circuitry structure opposite the second side;”. However, it is not understood from the claim language how a second side of the control circuitry structure is opposite to the same second side. For examination, the instant limitations will be considered as: “a memory array structure bonded to a first side of the control circuitry structure and comprising an array of memory cells; a bond pad overlying a second side of the control circuitry structure opposite the first side;” As claims 16-18 depend on the above rejected claim 13, they are also being rejected on the same reason. Allowable Subject Matter Claims 1-8 and 10-12 are allowed. Claims 13, 16-18 will be allowed after withdrawal of the above 112 rejection of claim 13. The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claim 1, the applicant has sufficiently claimed and defined a microelectronic device, whereby the prior arts of record and to the examiner's knowledge do not teach or render obvious, at least to the skilled artisan, the instant invention regarding the microelectronic device comprising: a control circuitry structure within a semiconductive material, having a bond pad on a backside and a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry, wherein an insulating slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the insulating slit. The closest prior art of record, Oh et al. (US 20210383874 A1, fig. 6) teaches, a control circuitry structure (LW2) within a semiconductive material (30), having a bond pad (130) on a backside and a conductive contact (51) vertically extending from the bond pad (130), through the semiconductive material (30), and to the control logic circuitry (37), wherein an insulating slit (50) vertically extending into the semiconductive material (30) and horizontally circumscribing the conductive contact (51), but fails to teach, wherein portions of the semiconductive material (30) horizontally interposed between the conductive contact (51) and the insulating slit (50). None of the prior arts of record, either singularly or in combination, can be used to modify the device of Oh et al. to teach the above missing feature with obvious motivation or without breaking the device of Oh et al. Regarding independent claim 13, the applicant has sufficiently claimed and defined a memory device, whereby the prior arts of record and to the examiner's knowledge do not teach or render obvious, at least to the skilled artisan, the instant invention regarding the memory device comprising: a control circuitry structure comprising control logic devices, having a bond pad on one side and one or more conductive contacts vertically extending from the bond pad, through a semiconductive material, and to the control logic devices, wherein dielectric structures vertically extending into the semiconductive material and horizontally circumscribing the one or more conductive contacts, portions of the semiconductive material horizontally intervening between the one or more conductive contacts and the dielectric structures. The closest prior art of record, Oh et al. (US 20210383874 A1, fig. 6) teaches, a control circuitry structure (LW2) comprising control logic devices (37), having a bond pad (130) on one side and one or more conductive contacts (51) vertically extending from the bond pad, through a semiconductive material (30), and to the control logic devices (37), wherein dielectric structures (50) vertically extending into the semiconductive material (30), but fails to teach, wherein portions of the semiconductive material (30) horizontally intervening between the one or more conductive contacts (51) and the dielectric structures (50). None of the prior arts of record, either singularly or in combination, can be used to modify the device of Oh et al. to teach the above missing feature with obvious motivation or without breaking the device of Oh et al. The dependent claims are allowed as they depend on the allowed independent claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 10, 2024
Application Filed
Jun 09, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 737 resolved cases by this examiner. Grant probability derived from career allowance rate.

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