Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 04/23/2026. Currently, claims 1-23 are pending in the application. Claims 4-5, 10-11, 14, 17-18 and 21 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Species I (Figures 1-11), claims 1-3, 6-9, 12-13, 15-16, 19-20 and 22-23, in the reply filed on 04/23/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6-7, 13, 15, 19-20 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DOORNBOS et al (US 20210375874 A1).
Regarding claim 1, Figure 14 of DOORSBOS discloses a semiconductor device comprising:
a substrate (8, [0039]);
a lower portion (18) of a first conductive pattern (18+23, [0054]) disposed over the substrate and extending in a second direction (X direction);
a stacked structure (23/25/27/14) disposed over the lower portion (18) of the first conductive pattern and having a pillar shape, the stacked structure including an upper portion (23) of the first conductive pattern, an oxide semiconductor channel (25, [0054]), and a second conductive pattern (27+14); and
a word line (26, [0064]) extending in a first direction (Z direction, please see Figure 17) intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel (25) with a gate insulating layer (24, [0063]) therebetween, wherein the first conductive pattern (18+23) includes a first conductive metal oxides (23, includes metal oxide, [0054]) and the lower portion of the first conductive pattern corresponds to a bit line (18 is bite line, [0053]), and the upper portion (23) of the first conductive pattern corresponds to a drain electrode (23 is drain, [0057]).
Regarding claim 3, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 1, wherein, in the first direction (Z), a width of the lower portion (18) of the first conductive pattern is greater than a width of the stacked structure (23/25/27/14).
Regarding claim 6, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 1, wherein the first conductive metal oxide includes ITO, In203, or a metallic oxide semiconductor ([0054]).
Regarding claim 7, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 1, wherein the second conductive pattern (27+14) includes a lower portion (27, [0054]) corresponding to a source electrode and an upper portion (14) corresponding to a lower electrode of a capacitor ([0064]).
Regarding claim 13, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 7, further comprising: a capacitor insulating layer (30, [0069]) surrounding a sidewall and a top surface of the upper portion (14) of the second conductive pattern (27+14); and an upper electrode (32, [0069]) of the capacitor formed over the capacitor insulating layer.
Regarding claim 15, Figure 14 of DOORSBOS discloses a semiconductor device comprising:
a substrate (8, [0039]);
a bit line (18, [0054]) disposed over the substrate and extending in a second direction (X);
a stacked structure (23/25/27/14) disposed over the bit line and having a pillar shape, the stacked structure including a drain electrode (23, [0057]), an oxide semiconductor channel (25, [0057]), and a conductive pattern (27+14); and
a word line (26/40, [0064]) extending in a first direction (Z) intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel (25) with a gate insulating layer (24, [0064]) therebetween, wherein the conductive pattern includes a conductive metal oxide (27contains metal oxide, [0054]), and a lower portion (27) of the conductive pattern corresponds to a source electrode, and an upper portion (14) of the conductive pattern corresponds to a lower electrode of a capacitor (104, [0069]).
Regarding claim 19, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 15, wherein the conductive metal oxide includes ITO, In203, or a metallic oxide semiconductor ([0054]).
Regarding claim 20, Figure 14 of DOORSBOS discloses that the semiconductor device according to claim 15, further comprising: a capacitor insulating layer (30, [0069]) surrounding a sidewall and a top surface of the upper portion (14) of the conductive pattern; and an upper electrode (32, [0069]) of the capacitor formed over the capacitor insulating layer.
Regarding claim 22, Figure 14 of DOORSBOS discloses a semiconductor device comprising:
a substrate (8, [0039]);
a first conductive pattern (18+23, [0054]) disposed over the substrate and extending in a second direction (X), the first conductive pattern consisting of a line shape bottom part (18) covering a top surface of the substrate (8), and a plurality of spaced apart pillar (23/25/27/14, only one showed but there are plurality of pillar in a memory device, [0002]) shape top parts rising over the line shape bottom part in a vertical direction;
a plurality of stacked structures (23/25/27/14), each stacked structure disposed over a corresponding one of the pilar shape top parts of the first conductive pattern and having a pillar shape, each stacked structure including an oxide semiconductor channel (25, [0057]), and a second conductive pattern (27+14) sequentially stacked; and
a word line (26/40, [0064]) extending in a first direction (Z) intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel (25) with a gate insulating layer (24, [0064]) therebetween.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 8-9, 12, 16 and 23 are rejected under 35 U.S.C. 103 as being obvious over DOORNBOS et al (US 20210375874 A1) in view of HWANG (US 20150079744 A1).
Regarding claims 2, 8, 16 and 23, Figure 14 of DOORSBOS does not explicitly teach that the semiconductor device according to claim 1, wherein there is no interface between the lower portion of the first conductive pattern and the upper portion of the first conductive pattern, or
The semiconductor device according to claim 7, wherein there is no interface between the lower portion of the second conductive pattern and the upper portion of the second conductive pattern.
The semiconductor device according to claim 15, wherein there is no interface between the lower portion of the conductive pattern and the upper portion of the conductive pattern.
The semiconductor device according to claim 22, wherein there is no interface between the line shape bottom part of the first conductive pattern and the pillar shape top parts of the first conductive pattern.
However, DOORSBOS teaches that a metal oxide can be used as an alternative to metal layers in 14 similar to the material of layer 27 ([0038] and [0067]). Further, HWANG is a pertinent art here teaches that a buried bit line 104 can be formed of a metal layer, a metal oxide layer, a metal nitride layer or a metal silicide layer for low resistance between source region and the bit line ([0027] of HWANG).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to metal oxide material in both 23 and 18 in the device of DOORSBOS instead of metal in layer 18 and metal oxide in layer 23 according to the teaching of DOORSBOS ([0038] and [0067]) and HWANG ([0027]) in order to reduce resistance between the source region 23 and 18 for improved device performance and lower cost, wherein there will be no interface between layer 23 and 18 in the device of Figure 14 of DOORSBOS. Further, it has been held to be within the general skill of a worker in the art to select a known material such as metal oxide instead of metal layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960). Moreover, the court has held that a simple substitution of one known element for another to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 9, Figure 14 of DOORSBOS in view of HWANG teach that the semiconductor device according to claim 7, wherein the second conductive pattern (27+14) includes a second conductive metal oxide ([0054] of DOORSBOS).
Regarding claim 12, Figure 14 of DOORSBOS in view of HWANG teach that the semiconductor device according to claim 9, wherein the second conductive metal oxide includes ITO, In203, or a metallic oxide semiconductor ([0054] of DOORSBOS).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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