DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/409,935, application filed on 01/11/2024. Claims 1-19 are currently pending in this application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 01/11/2024 and 09/24/2024, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-3, 5-7 and 9-19 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ogawa et al. (US PG Pub No. 2014/0181770).
6. With respect to independent claims 1 and 16, Ogawa teaches:
analyzing a printed circuit board (PCB) design (see printed substrate design, Abstract; see analyzing printed substrate design, para 15), the method comprising:
obtaining a PCB design file from a user (see design information for printed substrate, receiving input, para 86; see user setting input data, para 10), wherein the PCB design file comprises a design of a PCB;
determining electromagnetic compatibility (EMC) information of the PCB based on the design of the PCB of the obtained PCB design file (see determining whether printed substrate satisfies the EMI allowable condition, para 88, 90; see electromagnetic compatibility, para 93);
analyzing the EMC information to determine whether at least one EMC issue (see exceeding maximum value for common mode radiation, para 133) is detected in the EMC information (see EMI characteristic derivation unit, para 93; see EMI allowable condition is not satisfied, Abstract, para 95; see maximum EMI value characteristic does not satisfy the allowable EMI value characteristic, para 95); and
determining feedback information based on a result of the analyzing of the EMC information (after determining whether or not the determination criterion is satisfied, changing the substrate design, para 91; then repeat process using substrate information to achieve allowable pcb design, para 91).
7. With respect to claim 2, Ogawa teaches:
the method according to claim 1, further comprising:
in response to finding the at least one EMC issue in the EMC information (see exceeding maximum value for common mode radiation, para 133; see EMI characteristic derivation unit, para 93; see EMI allowable condition is not satisfied, Abstract, para 95), assigning a relevance value to the at least one detected EMC issue (see EMI [maximum] value characteristic of radiation for the printed substrate, and based extracted parameters of EMI information for printed substrate, para 95), and
determining whether the at least one detected EMC issue has a relevance value equal to or higher than a relevance threshold (compare EMI [maximum] value characteristic of radiation for the printed substrate to EMI allowable value characteristic, para 95),
wherein determine the feedback information is based on the detected EMC issues with the relevance value equal to or higher than the relevance threshold (see maximum value for common mode radiation exceeding the allowable EMI value characteristic, para 95).
8. With respect to claim 3, Ogawa teaches:
The method according to claim 1,
wherein the determined EMC information is performed by a human expert or by a static determination algorithm implemented on a computing device or by a machine learning determination algorithm implemented on a computing device (see EMI information extracted by means of a calculation parameter extraction process, para 53; see calculating EM radiation from a cable caused by common mode current, para 7, 93; see calculation unit, para 128), and/or
wherein analyzing the EMC information to determine whether the at least one EMC issue is detected in the EMC information is performed by a human expert or by a static analysis algorithm implemented on a computing device or by a machine learning analysis algorithm implemented on a computing device (see EMI information extracted by means of a calculation parameter extraction process, para 53; see calculating EM radiation from a cable caused by common mode current, para 7, 93; see calculation unit, para 90-93, 128l; comparison unit to compare EMI value to EMI allowable value, para 90-93, 128), and/or
wherein determining the feedback information is performed by a human expert or by a static feedback algorithm implemented on a computing device or by a machine learning feedback algorithm implemented on a computing device (see substrate configuration change unit which is responsible for changing the substrate design, para 91; then repeat process using substrate information to achieve allowable PCB design, para 91).
9. With respect to claim 5, Ogawa teaches:
The method according to claim 1, wherein the feedback information comprises a PCB health score comprising at least three health score levels, and/or wherein the feedback information comprises a probability whether an EMC certification test will be passed or not, and/or wherein the feedback information comprises suggestions that reduce a number of EMC issues in the EMC information and/or reduce a severity of the EMC issues in the EMC information (after determining whether or not the determination criterion is satisfied, changing the substrate design, para 91; then repeat process using substrate information to achieve allowable pcb design, para 91; see EMI condition determination unit designed to achieve a low EMI level, para 88).
10. With respect to claim 6, Ogawa teaches:
The method according to claim 1, further comprising:
determining at least one redesign of at least one part of the design of the PCB based on the feedback information (after determining whether or not the determination criterion is satisfied, changing the substrate design, para 91; then repeat process using substrate information to achieve allowable pcb design, para 91); and
outputting at least one updated PCB design file comprising the redesigned at least one part of the design of the PCB (an output unit that outputs a printed substrate configuration that satisfies an EMI allowable condition after the circuit/substrate is changed, Abstract).
11. With respect to claim 7, Ogawa teaches:
The method according to claim 6, wherein at least two redesigns of the at least one part of the design of the PCB are determined (see repeating steps that involve determining an allowable EMI condition, and if not allowable, making a change to the substrate until an allowable design is found, para 89-91).
12. With respect to claim 9, Ogawa teaches:
The method according to claim 1, wherein the determining EMC information comprises at least one of the following:
determining shielding information of at least one part of the PCB (see providing shielding effect on PCB, para 15),
determining grounding information of at least one part of the PCB (see information on ground layer and structure for pcb, para 106, 109, 119),
determining filtering information of at least one part of the PCB,
determining bypassing information of at least one part of the PCB,
determining signal integrity information of at least one part of the PCB (see electric current flowing through signal, and noise sources which can impact signal integrity, para 97),
determining Power Delivery Network information of at least one part of the PCB (see power delivery circuit for PCB, and power and ground planes, para 88-92),
determining emissions information of at least one part of the PCB (see EMI information as emissions of radiation information, Abstract, para 93), or
determining immunity information of at least one part of the PCB.
13. With respect to claim 10, Ogawa teaches:
The method according to claim 1, wherein determining the feedback information comprises at least one of the following:
determining an improved shielding technique of at least one part of the PCB (see providing shielding effect on PCB, para 15),
determining an improved grounding technique of at least one part of the PCB (see information on ground layer and structure for pcb, para 106, 109, 119),
determining an improved filtering technique of at least one part of the PCB, or
determining an improved bypassing technique of at least one part of the PCB.
14. With respect to claim 11, Ogawa teaches:
The method according to claim 1, further comprising:
adapting the PCB design according to the feedback information (after determining whether or not the determination criterion is satisfied, changing the substrate design, para 91); and
iteratively repeating determining the EMC information of the PCB, analyzing the EMC information and determining the feedback information with adapting the PCB design (then repeat process using substrate information to achieve allowable pcb design, para 91).
15. With respect to claim 12, Ogawa teaches:
The method according to claim 1, wherein analyzing the EMC information to determine whether the at least one EMC issue is detected in the EMC information is further based on at least one of the following:
an application case requirement for the PCB;
country information;
housing information;
cabling information information concerning other PCBs a system in which the PCB is to be used (see cabling for printed substrate, Abstract);
measurement results from prototypes;
information concerning previous design revisions (see information on previous processes, para 111); or
expertise information of a design engineer of the PCB.
16. With respect to claim 13, Ogawa teaches:
The method according to claim 1, wherein the method is a computer implemented method (see memory unit and data processing components, para 135-140).
17. With respect to claim 14, Ogawa teaches:
A computer program product comprising instructions which, when executed on a computing device, implements the method according to claim 1 (see memory unit and data processing components, para 135-140).
18. With respect to claim 15, Ogawa teaches:
A computer-readable storage medium comprising the computer program product according to claim 14 (see memory unit and data processing components, para 135-140).
19. With respect to claim 17, Ogawa teaches:
The system according to claim 16, further comprising:
a user device connected with the data processing device (see input unit, see design information for printed substrate, receiving input, para 86; see user setting input data, para 10), the user device being configured to:
send the PCB design file to the data processing device via a network (); and/or
provide user information to the data processing device (see input unit, see design information for printed substrate, receiving input, para 86; see user setting input data, para 10).
20. With respect to claim 18, Ogawa teaches:
The system according to claim 17, wherein the user device is further configured to run a user application which is used by the user to send the PCB design file to the data processing device and/or to provide the user information to the data processing device (see memory unit and data processing components, para 135-140).
21. With respect to claim 19, Ogawa teaches:
The system according to claim 16, further comprising an expert device configured to run an expert application via which expert information and/or background information is providable to the data processing device (see memory unit and data processing components, para 135-140).
Claim Rejections - 35 USC § 103
22. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
23. Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US PG Pub No. 2014/0181770) in view of Wang et al. (US PG Pub No. 2024/0428399).
24. With respect to claim 4, Ogawa appears to be silent regarding:
The method according to claim 3, further comprising:
training the respective machine learning algorithm based on expert information and/or user information and/or background information in response to performing any of the determining EMC information and/or the analyzing the EMC information and/or the determining feedback information by the respective machine learning algorithm.
However, Wang teaches:
training the respective machine learning algorithm based on expert information and/or user information and/or background information in response to performing any of the determining EMC information and/or the analyzing the EMC information and/or the determining feedback information by the respective machine learning algorithm (training model data for determining defects/problems of a PCB with respect to threshold values in for defects in PCB’s, para 3-4, 19).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated the machine-learning (ML) defect detection model of Wang into the invention of Ogawa for at least the following reasons: the ML training model of Wang improves the defect/problem detection process of Ogawa by expanding on the data used to detect or find issues/problems with the PCB.
25. With respect to claim 8, Ogawa appears to be silent regarding:
The method according to claim 1, further comprising establishing a communication channel between the user and an expert.
However, Wang teaches:
The method according to claim 1, further comprising establishing a communication channel between the user and an expert (see training data used in network interface to be used in defect location module to be provided to/from a user, para 53-54).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated the machine-learning (ML) defect detection model of Wang into the invention of Ogawa for at least the following reasons: the ML training model of Wang improves the defect/problem detection process of Ogawa by expanding on the data used to detect or find issues/problems with the PCB.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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