Prosecution Insights
Last updated: August 17, 2026
Application No. 18/409,950

WAFER HOLDER APPARATUS, SYSTEM AND METHOD OF FORMING SAME

Non-Final OA §103
Filed
Jan 11, 2024
Examiner
DODDS, SCOTT
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
567 granted / 829 resolved
+8.4% vs TC avg
Strong +35% interview lift
Without
With
+35.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
54 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
14.3%
-25.7% vs TC avg
§112
27.1%
-12.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 829 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Claims 1-10 and 21-30 in the reply filed on 6/17/2026 is acknowledged. Claim Objections Claim 29 objected to because of the following informalities: Claim 29 ends with “the receiving includes monitoring for a lateral shift of an edge of the semiconductor wafer using a light beam produced by the light interrupt sensor during the transferring of the semiconductor wafer from the first semiconductor processing tool to the se second semiconductor processing tool.” And should be amended: “the receiving includes monitoring for a lateral shift of an edge of the semiconductor wafer using a light beam produced by the light interrupt sensor during the transferring of the semiconductor wafer from the first semiconductor processing tool to the [[se]] second semiconductor processing tool.” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonora et al. (US 10,755,960) in view of Hsiao (US 6,546,307). Regarding Claim 29, Bonora et al. a semiconductor wafer transfer method comprising (See Abstract, wherein the transfer apparatus performs a transfer method): receiving a semiconductor wafer (See col. 1, lines 22-25, wherein the wafers discussed throughout are clearly semiconductors) in a semiconductor processing system using a wafer transfer assembly mounted to a robotic transfer arm (See col. 2, lines 51-55 and col. 5, lines 65-67, teaching a transfer apparatus for semiconductor wafer to transfer the wafer between desired locations while ensuring alignment during transfer, the transfer apparatus being a SCARA robot, i.e. robotic transfer arm); wherein the wafer transfer assembly includes at least one wafer holder and at least one light interrupt sensor [451] mounted on the wafer transfer assembly, and the receiving includes monitoring for a lateral shift of an edge of the semiconductor wafer using a light beam produced by the light interrupt sensor during the transferring of the semiconductor wafer (See Fig. 4a, col. 10, lines 35-57 and col. 15, lines 44-56, wherein a light interrupter sensor [451], i.e. called a break the beam sensor, on the wafer holding portion of the transport apparatus detects edge position of the wafer during transport to indicate misalignment, i.e. lateral shift, by “breaking the beam,” i.e. using a light interrupt sensor as claimed, to ensure alignment at the receiving location). The transport apparatus does not explicitly teach transfer between processing stations, but it is known to monitor alignment during this transfer as well and would have been apparent the device is useful for start of processing or between processing to ensure alignment, which is highly desired during semiconductor processing to ensure accuracy and precision (See, for example, Hsiao, col. 1, lines 19-37, wherein wafers are stored and transfer from station to station for process via handling equipment, and such equipment is known to use mounted light sensor to ensure accurate positioning, see col. 2, lines 16-52, wherein a light sensor on the transfer robot usable between transfer station or from the initial cassette stack is used to monitor wafer position/alignment via a light sensor that indicates improper positioning when blocked). Thus, it would have been obvious to a person having ordinary skill in the art at the time of invention to utilize as transfer robot as in Bonora et al. to monitor wafer position from supply to processing areas or from processing areas to subsequent processing area. It is well-known to process wafer through multiple station from which they require transfer and proper alignment and there is no reason a sensor such as in Bonora et al. wouldn’t have been advantageous to detect lateral shift between process stations to ensure the same required advantage, i.e. proper positioning for transfer to the processing station. Claim(s) 1, 2, 6-10, 21, 22, 26, 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka et al. (US 2011/0211825) in view of Bonora et al. and/or Hsiao. Regarding Claims 1, 9, 21, 28 and 29, Matsuoka et al. teaches a semiconductor wafer processing method comprising: using a coater of a coating and developing tool [S2], coating a semiconductor wafer with a photoresist layer (See page 1, paragraph [0005] and page 6, paragraph [0047], Figs. 1 and 6, wherein coating [B3],[B4] and developing [B1],[B2] in block S2 coat a film, which is a resist for use with a photomask, i.e. a photoresist); after the coating, transferring the semiconductor wafer from the coating and developing tool to a photolithography exposure scanner [S4]; using the photolithography exposure scanner, forming a latent image of a photomask in the photoresist layer (See Fig. 1, page 1, paragraph [0005], and page 8, paragraph [0065]-[0066], wherein a transfer arm, called interface arm [I], transfers the coated wafer to the exposure apparatus [S4], wherein it is implicitly exposed using a photomask as described in the background process for standard photolithography, thus forming the latent image as claimed; and note all wafer transfer between [S2] and [S4] is via interface arm [I]); after the forming, transferring the semiconductor wafer from the photolithography exposure scanner to the coating and developing tool; and using a developer of the coating and developing tool, developing the latent image to form openings in the photoresist layer (See page 1, paragraph [0003], wherein developing occurs after exposure, the same interface arms [I] handling transfer back to [S2] for development in [B1],[B2], see Fig. 6, it is implicit the photoresist pattern is used to form an image to etch opening since this is standard in the process and well-known to those in the art); wherein the transferring of the semiconductor wafer from the photolithography exposure scanner to the coating and developing tool includes: receiving the semiconductor wafer from the photolithography exposure scanner using a wafer transfer assembly mounted to a robotic transfer arm, and using the robotic transfer arm to send the semiconductor wafer from the robotic transfer arm to the coating and developing tool, wherein the wafer transfer assembly includes at least one wafer holder (See page 8, paragraphs [0062] and [0065]-[0066], wherein the interface arm [I], formed similarly to transfer arm [D1] is a robotic arm to hold, i.e. via a holder, and transfer wafers between processing locations, specifically [S2] and [S4]). Matsuoka et al. is directed towards the overall organization of the semiconductor coating and developing device, and does not provide detailed description of the wafer transfer robots, such as interface arm [I], and thus does not teach a light interrupt sensor. However, wafer transfer robots are well known for semiconductor processing to move wafers for processing and the holding portion would have preferrable had similar applicability to hold and transfer a wafer. It is well-known to monitor wafer alignment during wafer transfer both at the start of processing or between processing stations to ensure alignment, which is highly desired during semiconductor processing to ensure accuracy and precision, which will be compromised if a wafer is not correctly positioned on a holder when entering a processing area (See, for example, Hsiao, col. 1, lines 19-37, wherein wafers are stored and transfer from station to station for process via handling equipment, and such equipment is known to use mounted light sensor to ensure accurate positioning, see col. 2, lines 16-52, wherein a light sensor on the transfer robot usable between transfer station or from the initial cassette stack is used to monitor wafer position/alignment via a light sensor that indicates improper positioning when blocked; and wherein misalignment can cause damage and reduce process throughput, see col. 1, line 59 to col. 2, line 10). It would have been apparent known devices for tracking wafer alignment on wafer transfer devices would have predictably been obvious to implement in Matsuoka et al. in order to ensure the wafer does not become misplaced during transfer and thus get processed incorrectly or damaged, i.e. such as during exposure or developing. Bonora et al. teaches a robotic transfer arm (See col. 2, lines 51-55 and col. 5, lines 65-67, teaching a transfer apparatus for semiconductor wafer to transfer the wafer between desired locations while ensuring alignment during transfer, the transfer apparatus being a SCARA robot, i.e. robotic transfer arm); wherein the wafer transfer assembly includes at least one wafer holder and at least one light interrupt sensor [451] mounted on the wafer transfer assembly, and the receiving includes monitoring for a lateral shift of an edge of the semiconductor wafer using a light beam produced by the light interrupt sensor during the transferring of the semiconductor wafer (See Fig. 4a, col. 10, lines 35-57 and col. 15, lines 44-56, wherein a light interrupter sensor [451], i.e. called a break the beam sensor, on the wafer holding portion of the transport apparatus detects edge position of the wafer during transport to indicate misalignment, i.e. lateral shift, by “breaking the beam,” i.e. using a light interrupt sensor as claimed, to ensure alignment at the receiving location if the beam of light is broken or interrupted). Thus, it would have been obvious to a person having ordinary skill in the art at the time of invention to utilize a light interrupt sensor on the interface arm [I] in Matsuoka et al., as taught in Bonora et al., so as to monitor the wafer position for correct positioning and for potential misalignment during transfer between [S2] and [S4]. Doing so would have predictably ensured the wafer in the coating and development process is properly positioned as desired and does not misalign during transfer, thus decreasing the odds of damage or defectiveness in forming the resist image that may result from said misalignment or improper positioning. Regarding Claims 2, 6, 22, and 26, the light sensor [451] is connected to a controller and detects an edge of the wafer and if the beam of light is interrupted to determine inaccurate alignment, i.e. a threshold value, a visual and/or aural indication, i.e. an alarm condition, is generated (See col. 10, lines 35-57, col. 11, line 55 to col. 12, line 2, and col. 15, lines 44-56, wherein the edge sensor [451], which runs through a controller, detects misalignment of the wafer via beam breaking, i.e. less intensity of light to a threshold condition to determine a wafer shift, and generate visual or aural alarm conditions). Any less light the triggers the alarm when the beam is interpreted is a threshold condition as claimed. Such sensors are known to have emitter and detector as taught explicitly in Hsiao. Although the sensor direction is depicted as being horizontal, it would have been apparent the break-the-beam sensor could have been positioned in any orientation to detect the edge of the wafer, such parallel (on the side of) or orthogonal to the edge (above and below) such that the edge would move into the path of the beam. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice). Regarding Claim 7, Matsuoka et al. doesn’t teach the holder, but Bonora et al. teach the holder includes a pincette (See Fig. 2K and Fig. 6, clearly showing what is reasonably a pincette), thus indicating this a suitable holder shape for wafer transfer while monitoring position for accuracy. Regarding Claims 8 and 27, Matsuoka et al. teaches interface arm I rotates about the vertical axis, implicitly during the transfer it implement between [S2] and [S4] (See page 8, paragraph [0065]), and as described, the light interrupter sensor would predictably monitor during any transfer movement. Regarding Claim 10, the Examiner takes official notice in process such as Matsuoka et al., the pattern is essentially always used for etching or filling, and this is standard as a subsequent process step, and at the very least obvious since this is the entire purpose of forming the resist pattern, and numerous such examples can be provided upon request. See MPEP 2144.03. Allowable Subject Matter Claims 3-5, 23-25 and 30 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art teaches numerous sensors but provides no specific motivation to motivator frequency of interruption over time to generate an alarm signal, and instead monitor position and location in isolation. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Doki et al. (US 7,884,622), teaching photolithography transfer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT W DODDS whose telephone number is (571)270-7653. The examiner can normally be reached M-F 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Orlando can be reached at 5712705038. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCOTT W DODDS/Primary Examiner, Art Unit 1746
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Prosecution Timeline

Jan 11, 2024
Application Filed
Jul 13, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
99%
With Interview (+35.4%)
2y 11m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 829 resolved cases by this examiner. Grant probability derived from career allowance rate.

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