Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18410162 filed on 01/04/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of (species 1A with figure 2I) claims 1-10 in the reply filed on 6/29/2026 is acknowledged.
Claim Objections
Claim 9 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 8. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Allowable subject matter
Claim 5 is objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner' s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Nagai et al. (US Pat 2019/0221569).
With respect to dependent claim 5, the cited prior art does not anticipate or make obvious, inter alia, the step of: “the horizontal portion of the inverted U-shaped isolation layer has an air gap, and wherein the air gap extends along the extending directions of the first word line and the second word line and spans the bit line”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al. (US 2019/0221569 A1) in view of Lu et al. (US 2022/0302128 A1).
Regarding independent claim 1, Nagai et al. teach a semiconductor structure, comprising:
a substrate (figs. 1-4, element 10, [0040]) having a first active area (figs. 1-4, element 12, [0044]) and an adjacent second active area (figs. 1-4, element 12, [0044]);
a first word line (fig.1, element WL, [0045]) and a second word line (fig.1, element WL), disposed in the substrate;
a bit line (fig.1, element BL, [0040]) spanning the first word line and the second word line;
a first storage capacitor contact (figs. 1-4, element SC, [0040]) and a second storage capacitor contact (figs. 1-4, element SC, [0040]), formed on the first word line and the second word line, respectively, to be coupled to the first active area and the second active area, respectively,
wherein the first storage capacitor contact and the second storage capacitor contact are disposed on the same side of the bit line (fig. 1);
an insulating layer (figs. 1-4, element 50P, [0040]) disposed between the first storage capacitor contact and the second storage capacitor contact (figs. 1-4);
Nagai et al. do not explicitly disclose an inverted U-shaped isolation layer disposed in the insulating layer and spanning the bit line.
However, Lu et al. is a pertinent art which discloses a memory device comprising an inverted U-shaped isolation layer (fig. 21, element 80, [0090]) disposed in the insulating layer (fig. 22, element 100 [0100]) and spanning the bit line (fig. 22, element 51, 52 [0076]).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the semiconductor device of Nagai to include an isolation layer as taught by Lu in order to improve protection of the bit line structure [0091].
Regarding claim 2, Nagai et al. modified by Lu teach the semiconductor structure, wherein the inverted U- shaped isolation layer (figs. 21 & 22 of Lu, element 80) comprises a horizontal portion (figs. 21 & 22 of Lu, element 60 [0078]) and two extending portions (figs. 21 & 22 of Lu, element 20 on opposite sides of 51 & 52, [0055]), and wherein the two extending portions extend from two ends of the horizontal portion in a direction toward the substrate (figs. 21 & 22 of Lu).
Regarding claim 3, Nagai et al. modified by Lu teach the semiconductor structure, wherein the horizontal portion (fig. 21 of Lu, element top of 60 [0088]) of the inverted U-shaped isolation layer (fig. 21 of Lu, element 80 [0090]) covers a top surface of the bit line (fig. 22 of Lu, element top of 51, 52), and wherein the extending portions (figs. 21 & 22 of Lu, element 20 [both sides of 51 & 52]), of the inverted U-shaped isolation layer cover opposite sidewall surfaces of the bit line (figs. 21 & 22 of Lu, opposite sides of 51 & 52), respectively.
Regarding claim 4, Nagai et al. modified by Lu teach the semiconductor structure, wherein the horizontal portion (fig. 21 of Lu, element top of 60) of the inverted U-shaped isolation layer (figs. 21 & 22 of Lu indicating) extends in a direction same as the first word line and the second word line extend (fig. 10 of Lu), as viewed from a top-view perspective [0062].
Regarding claim 6, Nagai et al. modified by Lu teach the semiconductor structure, wherein the inverted U- shaped (fig. 21 & 22 of Lu indicating) isolation layer (fig. 22 of Lu, element 80, [0090]) extends from a top surface (fig. 22 of Lu, top of 100) of the insulating layer to a bottom surface (fig. 22 of Lu, bottom of 100) of the insulating layer (fig. 22 of Lu, element 100).
Regarding claim 7, Nagai et al. teach the semiconductor structure, further comprising: a first insulating spacer (fig. 2, element 60 [right side of left SC] [0043]) disposed between the first storage capacitor contact (figs. 1-4, element SC [left] [0040]) and the insulating layer (figs. 1-4, element 50P, [0040]); and
a second insulating spacer (fig. 2, element 60 [left side of right SC] [0043]) disposed between the second storage capacitor contact (figs. 1-4, element SC [right] [0040]) and the insulating layer.
Regarding claims 8 & 9, Nagai et al. modified by Lu teach the semiconductor structure, wherein the first insulating spacer, the second insulating spacer, and the inverted U-shaped isolation layer are made of same of material [0051 discloses that insulating spacer layer and inverted U-shaped layer can be made from the same materials].
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al. (US 2019/0221569 A1) in view of Lu et al. (US 2022/0302128 A1), further in view of Jeon et al. (US 2023/0061185 A1)
Regarding claim 10 (Original): Nagai et al. modified by Lu teach the semiconductor structure comprises the first storage capacitor contact (figs. 1-4, element SC [left]) and the second storage capacitor contact (figs. 1-4, element SC [right]).
Nagai et al. modified by Lu do not teach the storage capacitor contact have an upper conductive structure and a lower conductive structure, and wherein the upper conductive structure comprises a metal, and the lower conductive structure comprises polysilicon.
However, Jeon et al. is a pertinent art which discloses a memory device comprising the storage capacitor contact (fig. 3, element 120 [0057]) have an upper conductive structure (fig. 3, element 122 [0144]) and a lower conductive structure (fig. 3, element 121 [0144]), and wherein the upper conductive structure comprises a metal [0115], and the lower conductive structure comprises polysilicon [0115] [0165].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the memory device of Nagai and Lu to include two different types manufacturing material in upper and lower conductive structures as taught by Lu in order to improve performance and reliability of the memory device [0005].
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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