DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 4/28/26 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/28/26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hurbi et al., US Publication No. 2018/0356156 A1.
Hurbi anticipates:
1. A semiconductor apparatus, comprising (see figs. 6A, figs. 8A-8C, also see figs. 6B-7B):
a substrate (805);
a plurality of semiconductor devices (835, 820, 810) on the substrate and arranged along a horizontal direction; and
a heat radiation device (e.g. 600 in fig. 6A) on the plurality of semiconductor devices (e.g. See para. [0088], [0090] disclosing “A shared internal dividing wall 870 is illustrated, but arrangements such as those illustrated in FIGS. 6A-7B may also be employed… A shared internal dividing wall 872 is illustrated, but arrangements such as those illustrated in FIGS. 6A-7B may also be employed.” Thus, in the present interpretation fig. 6A is being employed.),
wherein the heat radiation device (600) includes a plurality of vapor chambers (610, 615), and
wherein the plurality of vapor chambers (610, 615) are spaced apart (e.g. by 660, thermally insulating chamber or gap) from one another in the horizontal direction and are disconnected from one another (e.g. See para. [0081], disclosing thermally insulating chamber or gap 660 may be vacuum filled or filled thermal insulating material.). See Hurbi at para. [0001] – [0105], figs. 1-11.
2. The semiconductor apparatus of claim 1, wherein a number of the plurality of vapor chambers (e.g. 610, 615 in fig. 6A corresponding to 840, 845, 842, 847in fig. 8) is the same as a number of the plurality of semiconductor devices (835, 820, 810).
3. The semiconductor apparatus of claim 1, wherein the plurality of semiconductor devices (835, 820, 810) include a first semiconductor device (820) and a second semiconductor device (835),
wherein, when viewed in a plan view, a first one of the plurality of vapor chambers (840) overlaps the first semiconductor device (820) and is non-overlapping with the second semiconductor device (835), fig. 8.
4. The semiconductor apparatus of claim 1, (see fig. 4) wherein the heat radiation device (400)includes a support structure (460a-d, 465a-d) in a first vapor chamber of the plurality of vapor chambers,
wherein the support structure includes a support pillar (460a-d, 465a-d), and
wherein a thickness of the support pillar (460a-d, 465a-d) is the same as a thickness of the first vapor chamber (410), para. [0075] – [0076].
8. The semiconductor apparatus of claim 1, (see fig. 6A) wherein the horizontal direction is a first horizontal direction, and wherein the heat radiation device (600) includes a first heat pipe channel (660; e.g. See para. [0081], disclosing thermally insulating chamber or gap 660 may be vacuum filled or filled thermal insulating material.) between two neighboring ones of the plurality of vapor chambers (610, 615), the first heat pipe channel (660) extending in a second horizontal direction that intersects the first horizontal direction (e.g. Element 660 is a three-dimensional object so it extends in three directions, including a second horizontal direction.).
9. The semiconductor apparatus of claim 8, wherein the plurality of vapor chambers include (see fig. 8):
a first row (e.g.. row of 830a, 810, 835b) including a first plurality of vapor chambers (842, 847) arranged in the first horizontal direction; and
a second row (e.g. row of 820a, 810, 820b) including a second plurality of vapor chambers (840, 845) arranged in the first horizontal direction, wherein the second row is spaced apart from the first row in the second horizontal direction (e.g. See fig. 8A showing two rows spaced apart.)
10. The semiconductor apparatus of claim 9, wherein the heat radiation device comprises a second heat pipe channel (e.g. Figs. 8B and 8C show two dividing walls 870 and 872. Employing the thermally insulating chamber or gap 660 of fig. 6A per the disclosure at para. [0088], [0090] means there are two heat pipe channels where walls 870 and 872 are disposed.) between the first row and the second row,
wherein the first heat pipe channel is connected (e.g. through intervening layers) to the second heat pipe channel.
Regarding claim 11:
Hurbi teaches the limitations as applied to claims 1 and 8 above.
Hurbi further teaches:
12. The semiconductor apparatus of claim 11, wherein
each of the plurality of vapor chambers (610, 615) is disconnected from the heat pipe channel (660; e.g. See para. [0081], disclosing thermally insulating chamber or gap 660 may be vacuum filled or filled thermal insulating material.), and
each of the plurality of vapor chambers (610, 615) is separated from the heat pipe channel (660), fig. 6A..
13. The semiconductor apparatus of claim 11, wherein a width in the first horizontal direction of each of the plurality of vapor chambers (e.g. 840, 845, 842, 847 in fig. 8 corresponding to 610, 615 in fig. 6) is greater than a width in the first horizontal direction of the heat pipe channel (660 in fig. 6A)
14. The semiconductor apparatus of claim 11, wherein a thickness of each of the plurality of vapor chambers (610, 615) is constant across each of the plurality of vapor chambers in the first horizontal direction, fig. 6A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hurbi, as applied to claim 1 above, in view of Jeffers et al., US Publication No. 2022/0087066.
Regarding claim 5:
Hurbi teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the support structure includes a plurality of support plates coupled to the support pillar, and
wherein the plurality of support plates are spaced apart from one another circumferentially around the support pillar,
In an analogous art, Jeffers teaches:
5. The semiconductor apparatus of claim 4, (see figs. 1-2) wherein the support structure (103) includes a plurality of support plates (e.g. 103 radial plates) coupled to the support pillar (e.g. 103 center around 203), and
wherein the plurality of support plates (e.g. 103 radial plates) are spaced apart from one another circumferentially around the support pillar (e.g. 103 center around 203), para. [0039] – [0047].
Jeffers further teaches:
6. The semiconductor apparatus of claim 4, wherein, when viewed in a plan view, the support pillar (e.g. 103 center around 203) is at a center of the first vapor chamber (101), para. [0039] – [0047].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Hurbi with the teachings of Jeffers because “The variation in the width of the duct 103 can help to control the flow of working fluid in the vapour chamber 101… Having the ducts 103 extend radially outwards from the evaporator region 203 reduces the length of the ducts 103 that are required to provide the working fluid to the evaporator region 203. This minimizes the distance that the working fluid needs to travel.” See Hurbi at para. [0043] – [0044].
Claim(s) 7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hurbi, as applied to claim 1 above, in view of Ku et al., US Publication No. 2019/0385929 A1.
Regarding claim 7:
Hurbi teaches all the limitations of claim 1 above, but does not expressly teach:
an adhesion layer between the heat radiation device and each of the plurality of semiconductor devices,
wherein the adhesion layer is in contact with an entirety of a top surface of a first semiconductor device of the plurality of semiconductor devices.
In an analogous art, Ku teaches:
7. The semiconductor apparatus of claim 1, (see figs. 1A-1B) comprising an adhesion layer (131) between the heat radiation device (131) and each of the plurality of semiconductor devices (115, 117),
wherein the adhesion layer (131) is in contact with an entirety of a top surface of a first semiconductor device (115) of the plurality of semiconductor devices (115, 117). See Ku at para. [0026] – [0030], para. [0041] – [0043].
Regarding claim 15:
Ku further teaches:
15. The semiconductor apparatus of claim 11, comprising an edge adhesion layer (111) at an edge of the substrate (103),
wherein a top surface of the edge adhesion layer (111) is in contact (e.g. through 127/129) with the heat radiation device (131)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Hurbi with the teachings of Ku because (i) The adhesion layer such as a thermal interface material can be used “to improve electrical and/or thermal conduction by filling in microscopic air pockets created between minutely uneven surfaces” (e.g. See Ku at para. [0027], also see para. [0030], (ii) The edge adhesion allows the attachment of a vapor chamber ring (e.g. Ku at para. [0033])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
1 July 2026
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