DETAILED ACTION
This Office Action is responsive to the Applicant’s communications filed 11 January 2024 and 22 June 2026. In view of this communication, claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 22 June 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4, 6-7, 9-10, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20140102772 A1), hereinafter referred to as Chen et al, in view of Yamauchi et al. (US 20200402880 A1), hereinafter referred to as Yamauchi et al.
Regarding claim 1, Chen et al. teaches a semiconductor memory device assembly, comprising: a printed circuit board (PCB) (100a) (Fig. 2, paragraph 0041) including:
a reference layer (110) (paragraph 0009: dielectric layer in which the interposer is embedded);
a contact pad (124) (paragraph 0033: second pads 124 on the second surface of the interposer 120) over the reference layer (110) (paragraph 0009: dielectric layer 110 in which the interposer 120 is embedded), wherein the contact pad (124) includes metallic material (paragraph 35: the material of the pads 122, 124 and vias 127 are a conductive material) for electrically coupling the PCB to a circuit device (210) (paragraph 46: chip 210 electrically connected to the pads 124 via solder balls 220a) mounted thereon;
a solder resist layer (180a) (paragraph 0043: solder resist layer 180a formed on adhesive 130a which is formed on insulating layer 110) over the reference layer (110) and peripheral portions of the contact pad (124) (paragraph 0043: solder resist layer 180a has openings 182a corresponding to the contact pads 124), the solder resist layer (180a) including a solder opening (182a) exposing a middle portion of the contact pad (124) (paragraph 0043: openings 182a in solder resist layer 180a expose the pads 124 via the openings 132a in the adhesive layer 130a);
a delamination reduction mechanism (130a) disposed between the solder resist layer (180a) and the peripheral portions of the contact pad (124) (Fig. 2 and paragraph 0041: the openings 132a in the adhesive layer 130a expose the pads 124), and solder (220a) directly contacting the exposed middle portion of the contact pad (124) and within the solder opening (182a) (paragraph 0047: the solder 220a is disposed in openings 182a to contact second pads 124); and
a semiconductor device (210) mounted on the PCB (100a) (paragraph 0046: chip 210 disposed on packaging carrier 100a), the semiconductor device (210) including a connector portion extending from a bottom surface of the semiconductor device (210) and electrically coupled and affixed to the solder (220b) (paragraph 0046: chip 210 is electrically connected to the pads 124 via solder 220b).
Chen et al. does not teach that the delamination reduction mechanism has bonding strengths relative to the solder resist layer and the contact pad that are greater than a bonding strength between the metallic material of the contact pad and the solder resist layer. Yamauchi et al. does teach that the delamination reduction mechanism (60) has bonding strengths relative to the solder resist layer (120) and the contact pad (34) that are greater than a bonding strength between the metallic material of the contact pad (34) and the solder resist layer (120) (Yamauchi et al. Fig. 3B and paragraphs 0061-0062: adhesive layer 60 improves adhesion between sealing resin 120 and contact pad 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a material for the delamination reduction mechanism of Chen et al. that has the characteristics disclosed by Yamauchi et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Regarding claim 2, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, wherein the delamination reduction mechanism (130) (paragraph 0042: adhesive layer 130a) is an adhesion promoter configured to have a dual functionality for attaching to both organic and inorganic materials (paragraph 0041: adhesion layer 130a is a resin which can adhere to organic and inorganic materials).
Regarding claim 4, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, wherein the adhesion promoter (130a) and the solder resist layer (180a) have different mechanisms for removing and shaping the corresponding materials (paragraph 0056: holes 132a in adhesion layer 130a are formed by etching; paragraph 0043: the solder resist layer 180a is formed with holes 182a).
Regarding claim 6, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, wherein the solder opening (182a) is defined by one or more walls that extend continuously and linearly between a top surface of the solder resist layer (130a) and the contact pad (124) (Fig. 6 and paragraph 0043).
Regarding claim 7, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 6, wherein the continuous and linear walls are characteristic of having the delamination reduction mechanism disposed between the contact pad (124) and the solder resist layer (130a) before formation of the solder opening (182a) for reducing occurrences of a mask undercut that provides a lifting force on the solder resist layer (180a) and away from the contact pad (124) during solder reflow (Fig. 6 and paragraph 0043: adhesive layer 130a disposed between the contact pad 124 and the solder resist layer 180a).
Regarding claim 9, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, wherein the delamination reduction mechanism (130a) is disposed between the solder resist layer (180a) and the contact pad (124) at the solder opening (132a) for reducing a likelihood of delamination of the solder resist layer (180a) from the reference layer (110) based on increasing a relative bonding strength between the solder resist layer (180a) and the contact pad (124) at the solder opening (132a) that experiences pressure during reflowing of the solder (paragraph 0041: adhesive layer 130a improves adhesion between solder resist layer 180a and insulating layer 110).
Regarding claim 10, Chen et al. teaches a substrate, comprising
a reference layer (110) (paragraph 0009: dielectric layer in which the interposer is embedded);
a set of contact pads (124) (paragraph 0033: second pads 124 on the second surface of the interposer 120) over the reference layer (110) (paragraph 0009: dielectric layer 110 in which the interposer 120 is embedded), wherein the contact pads (124) are configured to electrically couple the substrate (110) to one or more corresponding circuit devices (210) mounted thereon (paragraph 46: chip 210 electrically connected to the pads 124 via solder balls 220a);
a solder resist layer (180a) (paragraph 0043: solder resist layer 180a formed on adhesive 130a which is formed on insulating layer 110) over and covering the reference layer (110) and peripheral portions of the contact pads (124) (paragraph 0043: solder resist layer 180a has openings 182a corresponding to the contact pads 124), the solder resist layer (180a) including solder openings (182a) exposing middle portions of the contact pads (124) (paragraph 0043: openings 182a in solder resist layer 180a expose the pads 124 via the openings 132a in the adhesive layer 130a);
a delamination reduction mechanism (130a) disposed between the solder resist layer (180a) and the peripheral portions of the contact pads (124) (paragraph 0047: the solder 220a is disposed in openings 182a to contact second pads 124); and
solder (220a) directly contacting the exposed middle portions of the contact pads (124) and within the solder openings (182a) (paragraph 0047: solder balls 220a in the openings 182a).
Chen et al. does not teach that the delamination reduction mechanism has bonding strengths to the solder resist layer and the contact pad that exceed a bonding strength between the contact pads and the solder resist layer. Yamauchi et al. does teach that the delamination reduction mechanism has bonding strengths to the solder resist layer and the contact pad that exceed a bonding strength between the contact pads and the solder resist layer (Yamauchi et al. Fig. 3B and paragraphs 0061-0062: adhesive layer 60 improves adhesion between sealing resin 120 and contact pad 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a material for the delamination reduction mechanism of Chen et al. that has the characteristics disclosed by Yamauchi et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Regarding claim 13, Chen et al. in view of Yamauchi et al. teaches the substrate of claim 10, wherein each of the solder openings (182a) is defined by one or more walls that extend from a top surface of the solder resist layer (180a) to a corresponding one of the middle portions of the contact pads (124) (Fig. 6 and paragraph 0043).
Regarding claim 14, Chen et al. in view of Yamauchi et al. teaches the substrate of claim 13, wherein the one or more walls for the each of the solder openings (182a) extends vertically or inwardly toward the corresponding one of the middle portions of the contact pads (124) (Fig. 6 and paragraph 0043).
Regarding claim 15, Chen et al. in view of Yamauchi et al. teaches the substrate of claim 14, wherein the one or more walls are characteristic of having the delamination reduction mechanism (130a) disposed between the contact pad (124) and the solder resist layer (180a) before formation of the solder openings (182a) for reducing occurrences of mask undercuts that extend downward and laterally away from the middle portions of the contact pads (124) and the corresponding lifting forces on the solder resist layer (180a) during solder reflow (Fig. 6 and paragraph 0043: adhesive layer 130a disposed between the contact pad 124 and the solder resist layer 180a).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Yamauchi et al., in further view of Ono et al. (US 6217987 B1), hereinafter referred to as Ono et al. and Ko et al. (US 20200105694 A1), hereinafter referred to as Ko et al.
Regarding claim 3, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, but does not teach that the reference layer is a prepreg layer; the contact pad includes copper; the solder resist layer includes polymer material; and the adhesion promoter is configured for attaching to both the copper and the polymer materials.
Ono et al. teaches that the contact pad includes copper (Ono et al. column 6, lines 10-15); the solder resist layer includes polymer material (Ono et al. claim 10); and the adhesion promoter is configured for attaching to both the copper and the polymer materials.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the contact pad of copper and the solder resist of a polymer as taught by Ono et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Ko et al. does teach that the reference layer is a prepreg layer (Ko et al. paragraph 119: the insulating layer 111c may be formed of a prepreg).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the reference layer of Chen et al. in view of Yamauchi et al. from a prepreg as taught by Ko et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Yamauchi et al., in further view of Gardner et al. (US 20220361323 A1), hereinafter referred to as Gardner et al.
Regarding claim 5, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, wherein the PCB includes a set of contact pads (124) (paragraph 0035) including the contact pad (124), for coupling with the semiconductor device (210).
Chen et al. in view of Yamauchi et al. does not teach that the contact pads are arranged according to a pitch corresponding to a maximum lateral separation distance between adjacent contact pads, wherein the maximum lateral separation distance is 500µm. Gardner et al. does teach that that the contact pads are arranged according to a pitch corresponding to a maximum lateral separation distance between adjacent contact pads, wherein the maximum lateral separation distance is 500µm (Gardner et al. paragraph 215).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the contact pads of Chen et al. in view of Yamauchi et al. with a maximum lateral separation of 500µm as taught by Gardner et al. because it has been held that the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Yamauchi et al., in further view of Sato et al. (US 20090102062 A1), hereinafter referred to as Sato et al.
Regarding claim 8, Chen et al. in view of Yamauchi et al. teaches the assembly of claim 1, but does not teach a trace over and extending laterally across at least a portion of the reference layer, the trace electrically coupled to the contact pad and configured to route one or more signals to and/or from the contact pad to one or more other circuits, wherein the delamination reduction mechanism is a layer disposed between and directly contacting the solder resist layer and a combination of the reference layer, a portion of the contact pad, and the trace.
Sato does teach a trace (20) (Fig. 3, paragraph 0041: wirings 20) over and extending laterally across at least a portion of the reference layer (30) (paragraph 0049: insulating layer 30), the trace (20) electrically coupled to the contact pad (52) and configured to route one or more signals to and/or from the contact pad (52) to one or more other circuits, wherein the delamination reduction mechanism (54) is a layer disposed between and directly contacting the solder resist layer and a combination of the reference layer, a portion of the contact pad, and the trace (paragraph 0080-0081 and 0083).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a trace such as that taught by Sato et al. on the reference layer of Chen et al. in view of Yamauchi et al. in order to provide additional connections to other circuits and electrical devices on the circuit board (Sato et al. Fig. 11C, paragraph 0041).
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that the delamination reduction mechanism is an adhesion promoter configured to have a dual functionality for attaching to both an organic material in the polymer material and an inorganic material in the metallic material to increase an overall bonding strength between the solder resist layer and the contact pads.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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