DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 5-10 and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. ALLOWABLE SUBJECT MATTER
Claims 1-4 and 11-15 are allowed .
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over NIU et al. (US Pub.: 2024/0063200) in view of Leon (US Pub.: 2014/0215141), Yoshihara et al. (US Pub. 2023/0187413), and Pawlowski (US Pub.: 2021/0200445).
As per claim 5, NIU teaches/suggests a high-bandwidth memory (HBM) device comprising: a plurality of first memory dies configured in accordance with a first architecture in which a first set of the plurality of first memory dies and a second set of the plurality of first memory dies are operating accordingly (e.g. associated with first die stack being a corresponding type of memory/storage die, wherein first die stack include a first set and a second set: Fig. 2E; and [0042]); and a plurality of second memory dies configured in accordance with a second architecture in which each memory die of the plurality of second memory dies is operating accordingly (e.g. associated with second die stack being a corresponding type of memory/storage die: Fig. 2E; and [0042]), and wherein at least one of the first memory dies or the second memory dies is configurable to operate accordingly (e.g. associated with the first die stack or the second die stack being configured to operate accordingly: Fig. 2E; and [0041]-[0043]) (Fig. 1; Fig. 2E; [0020]-[0028]; and [0041]-[0047]).
NIU does not teach the high-bandwidth memory (HBM) device comprising:
having an 8N architecture in which dies associated with different ones of a plurality of pseudo channels for a first channel; and
having a 4N architecture in which die is associated with a plurality of pseudo channels for a second channel, and
operating in accordance with the 8N architecture and the 4N architecture.
Leon teaches/suggests a storage device comprising: having an 8N architecture (e.g. associated with accessing memory chips via 8 word width: [0058]); and having a 4N architecture (e.g. associated with accessing memory chips via 4 word width: [0058]), and operating in accordance with the 8N architecture and the 4N architecture (e.g. associated with memory chips may be configure for accessing as 8 word width and 4 word width: [0056]-[0060]) ([0045]-[0058]; and [0056]-[0060]).
Yoshihara teaches/suggests a device comprising: architecture in which dies associated with different ones of a plurality of channels for a first channel; and architecture in which die is associated with a plurality of channels for a second channel (Fig. 2(a)-2(b); [0006]-[0007]; and [0041]-[0044]).
Pawlowski teaches/suggests a device comprising: operating with pseudo channels; and operating with pseudo channels ([0045]; and [0049]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Leon’s accessing of stacked architecture into NIU’s stacked architectures for the benefit of implementing a robust architecture with low parasitics and low power consumption (Leon, [0046]), enabling the accessing of a large number of storage transistor concurrently and in parallel (Yoshihara, [0044]), and increasing bandwidth while insuring command information did not get corrupted (Pawlowski, [0017]; and [0045]) to obtain the invention as specified in claim 5.
As per claim 7, NIU, Leon, Yoshihara and Pawlowski teach/suggest all the claimed features of claim 5 above, where NIU, Leon, Yoshihara and Pawlowski further teach/suggest the HBM device comprising: wherein the at least one of the first memory dies or the second memory dies comprises control logic configured to configure the at least one of the first memory dies or the second memory dies to operate in accordance with the 8N architecture in a first configuration and in accordance with the 4N architecture in a second configuration (e.g. associated with access via 8 word width and 4 word width) (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]).
As per claim 8, NIU, Leon, Yoshihara and Pawlowski teach/suggest all the claimed features of claim 7 above, where NIU, Leon, Yoshihara and Pawlowski further teach/suggest the HBM device comprising wherein: the control logic comprises one or more multiplexers; and the control logic is configurable between the first configuration and the second configuration based on inputs to the one or more multiplexers (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above multiplexer for multiplexing data to the corresponding memory die/chip.
As per claim 9, NIU, Leon, Yoshihara and Pawlowski teach/suggest all the claimed features of claim 8 above, where NIU, Leon, Yoshihara and Pawlowski further teach/suggest the HBM device comprising wherein at least one of the inputs to the one or more multiplexers comprises a most significant bit of a bank address of an addressed bank of the first memory dies or the second memory dies (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for accessing the memory dies/chips.
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over NIU et al. (US Pub.: 2024/0063200) in view of Leon (US Pub.: 2014/0215141), Yoshihara et al. (US Pub. 2023/0187413), and Pawlowski (US Pub.: 2021/0200445) as applied to claims 5 and 8, and further in view of O (US Pub.: 2021/0225430).
As per claims 6 and 10, NIU, Leon, Yoshihara and Pawlowski teach/suggest all the claimed features of claim 8 above, where NIU, Leon, Yoshihara and Pawlowski further teach/suggest the HBM device comprising: wherein the plurality of first memory dies are operating accordingly and the plurality of second memory dies are accordingly; and wherein at least one of the inputs to the one or more multiplexers comprises data associated with the at least one of the plurality of first memory dies or at least one of the plurality of second memory dies (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for accessing the memory dies/chips, but NIU, Leon, Yoshihara and Pawlowski do not teach the HBM device comprising: associated with a first stack identifier and associated with a second stack identifier; and operating with a bit of a stack identifier.
O teaches/suggests a device comprising: associated with a first stack identifier and associated with a second stack identifier; and operating with a bit of a stack identifier ([0015]; and [0020]) (Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include O’s architecture into NIU, Leon, Yoshihara and Pawlowski’s device for the benefit of efficiently use limited bus bandwidth for high speed data processing (O, [0009]) to obtain the invention as specified in claims 6 and 10.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over NIU et al. (US Pub.: 2024/0063200) in view of O (US Pub.: 2021/0225430), Leon (US Pub.: 2014/0215141), Yoshihara et al. (US Pub. 2023/0187413), and Pawlowski (US Pub.: 2021/0200445).
As per claim 16, NIU teaches/suggests a method comprising: transmitting, via an interface of a high-bandwidth memory (HBM) device, to a memory die of the HBM device (e.g. associated with transmission for read/write operation to the memory die via corresponding interface: [0020]-[0026]; [0043]); transmitting, via an interface of the HBM device, to the memory die of the HBM device (e.g. associated with transmission for read/write operation to the memory die via corresponding interface: [0020]-[0026]; [0043]), wherein the memory die is configured accordingly in which the memory die is operating accordingly and the memory die is (Fig. 1; Fig. 2E; [0020]-[0028]; and [0041]-[0047]).
NIU does not teach the method comprising:
operating, from an interface die, with a first memory bank on die, and using a first command address bus, signaling that causes the first memory bank to return first data on a first DQ bus;
in response to transmitting the signaling that causes the first memory bank to return the first data on the first DQ bus, receiving, at the interface die and using the first DQ bus, the first data;
operating, with the interface die, with a second memory bank on die, and using the first command address bus, signaling that causes the second memory bank to return second data on a second DQ bus, wherein the second memory bank is different from the first memory bank and the second DQ bus is different from the first DQ bus; and
in response to transmitting the signaling that causes the second memory bank to return the second data on the second DQ bus, receiving, at the interface die and using the second DQ bus, the second data,
operating in accordance with a 4N architecture in which (i) the first memory bank of die is associated with a first pseudo channel of a plurality of pseudo channels for a channel and (ii) the second memory bank of die is associated with a second pseudo channel of the plurality of pseudo channels for the channel.
O teaches/suggests a method comprising: operating, from an interface die (e.g. associated with interface between buffer die (1900) and memory die (1100)), with a first memory bank (e.g. associated with BK0 on BG0 in Fig. 5) on die, and using a first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7), signaling that causes the first memory bank to return first data on a first DQ bus (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056]); in response to transmitting the signaling that causes the first memory bank to return the first data on the first DQ bus, receiving, at the interface die and using the first DQ bus, the first data (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056]); operating, with the interface die (e.g. associated with interface between buffer die (1900) and memory die (1100)), with a second memory bank on die (e.g. associated with BK0 on BG2 in Fig. 5), and using the first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7), signaling that causes the second memory bank to return second data on a second DQ bus (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056]), wherein the second memory bank is different from the first memory bank (e.g. associated with BK0 on BG0 being different from BK0 on BG2 in Fig. 5) and the second DQ bus is different from the first DQ bus (e.g. associated with DB1 being different from DB0 in Fig. 5); and in response to transmitting the signaling that causes the second memory bank to return the second data on the second DQ bus, receiving, at the interface die and using the second DQ bus, the second data (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056]), architecture in which (i) the first memory bank of die is associated with a channel and (ii) the second memory bank of die is associated with the channel ([0007]-[0008]) (Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0007]-[0008]; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]).
Leon teaches/suggests a method comprising: operating in accordance with a 4N architecture (e.g. associated with accessing memory chips via 4 word width: [0058]) ([0045]-[0058]; and [0056]-[0060]).
Yoshihara teaches/suggests a method comprising: operating with a first channel of a plurality of pseudo channels and operating with a second channel of the plurality of channels (Fig. 2(a)-2(b); [0006]-[0007]; and [0041]-[0044]).
Pawlowski teaches/suggests a method comprising: operating with a pseudo channel and operating with a pseudo channel ([0045]; and [0049]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include O’s communicating architecture and Leon’s accessing of stacked architecture into NIU’s method for the benefit of efficiently use limited bus bandwidth for high speed data processing (O, [0009]), implementing a robust architecture with low parasitics and low power consumption (Leon, [0046]), enabling the accessing of a large number of storage transistor concurrently and in parallel (Yoshihara, [0044]), and increasing bandwidth while insuring command information did not get corrupted (Pawlowski, [0017]; and [0045]) to obtain the invention as specified in claim 16.
As per clam 17, NIU, O, Leon Yoshihara, and Pawlowski teach/suggest all the claimed features of claim 16 above, where NIU, O, Leon Yoshihara, and Pawlowski further teach/suggest the method comprising: transmitting, from the interface die of the HBM device, to a third memory bank on a second memory die (e.g. associated with BK0 on BG0 in memory die (1200) of O) of the HBM device, and using the first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7 of O), signaling that causes the third memory bank to return third data on the first DQ bus (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O); in response to transmitting the signaling that causes the third memory bank to return the third data on the first DQ bus, receiving, at the interface die and using the first DQ bus, the third data (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O); transmitting, from the interface die of the HBM device, to a fourth memory bank on the second memory die (e.g. associated with BK1 on BG0 in memory die (1200) of O) of the HBM device, and using the first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7 of O), signaling that causes the fourth memory bank to return fourth data on the first DQ bus (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O), wherein the fourth memory bank is different from the third memory bank (e.g. associated with BK0 on BG0 being different from BK1 on BG0 in memory die (1200) of O); and in response to transmitting the signaling that causes the fourth memory bank to return the fourth data on the first DQ bus, receiving, at the interface die and using the first DQ bus, the fourth data (e.g. associated with reading data that is returned on DB0 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O) (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; O, Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0007]-[0008]; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]).
As per clam 18, NIU, O, Leon Yoshihara, and Pawlowski teach/suggest all the claimed features of claim 17 above, where NIU, O, Leon Yoshihara, and Pawlowski further teach/suggest the method comprising: transmitting, from the interface die of the HBM device, to a fifth memory bank on a third memory die (e.g. associated with BK0 on BG2 in memory die (1300) of O) of the HBM device, and using the first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7 of O), signaling that causes the fifth memory bank to return fifth data on the second DQ bus (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O); in response to transmitting the signaling that causes the fifth memory bank to return the fifth data on the second DQ bus, receiving, at the interface die and using the second DQ bus, the fifth data (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O); transmitting, from the interface die of the HBM device, to a sixth memory bank on the third memory die (e.g. associated with BK1 on BG2 in memory die (1300) of O) of the HBM device, and using the first command address bus (e.g. associated with command and address signal CA being communicated via corresponding bus in Fig. 7 of O), signaling that causes the sixth memory bank to return sixth data on the second DQ bus (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O), wherein the fifth memory bank is different from the sixth memory bank (e.g. associated with BK0 on BG2 being different from BK1 on BG2 in memory die (1300) of O); and in response to transmitting the signaling that causes the sixth memory bank to return the sixth data on the second DQ bus, receiving, at the interface die and using the second DQ bus, the sixth data (e.g. associated with reading data that is returned on DB1 in Fig. 5: [0026]; [0033]-[0034]; [0037]; [0040]; [0043]; [0053]; [0056] of O) (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; O, Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0007]-[0008]; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]).
As per clam 19, NIU, O, Leon Yoshihara, and Pawlowski teach/suggest all the claimed features of claim 18 above, where NIU, O, Leon Yoshihara, and Pawlowski further teach/suggest the method comprising: wherein the second memory die and the third memory die are configured in accordance with an 8N architecture (e.g. associated with using 8 word width for data accessing: [0058]) (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; O, Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0007]-[0008]; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]; and Leon, [0045]-[0058]; [0056]-[0060]).
As per clam 20, NIU, O, Leon Yoshihara, and Pawlowski teach/suggest all the claimed features of claim 18 above, where NIU, O, Leon Yoshihara, and Pawlowski further teach/suggest the method comprising: wherein: transmitting the signaling that causes the first memory bank to return the first data on the first DQ bus comprises identifying the first memory die by at least a first stack identifier (e.g. associated with stack identifier SID0/SID1: [0015]; [0020] of O); transmitting the signaling that causes the third memory bank to return the third data on the first DQ bus comprises identifying the second memory die at least by a second stack identifier different from the first stack identifier (e.g. associated with stack identifier SID0/SID1: [0015]; [0020] of O); and transmitting the signaling that causes the fourth memory bank to return the fourth data on the second DQ bus comprises identifying the third memory die by at least the second stack identifier (e.g. associated with stack identifier SID0/SID1: [0015]; [0020] of O) (NIU, Fig. 1; Fig. 2E; [0020]-[0028]; [0041]-[0047]; O, Fig. 1-3; Fig. 5; Fig. 7; Fig. 9; [0007]-[0008]; [0012]-[0030]; [0032]-[0037]; [0040]-[0043]; [0053]; [0056]; Leon, [0045]-[0058]; [0056]-[0060]; Yoshihara, Fig. 2(a)-2(b); [0006]-[0007]; [0041]-[0044]; and Pawlowski, [0045]; [0049]).
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 April 20, 2026
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