DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/06/2026 have been fully considered but they are not persuasive.
It is argued by applicant that Wu does not discloses "an inner spacer including a gap above the highest channel and laterally between the upper portion of the gate metal and the source/drain region."
Examiner is not persuaded because Wu discloses the limitations as labeled by examiner below.
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Applicant’s arguments with respect to other amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the gaps” lacks antecedent basis. As such it is unclear and indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. 20230123484
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Regarding claim 1, fig. 4D of Lin discloses a device, comprising:
a transistor including:
a plurality of stacked channels 106;
a source/drain region 139 (par [0048]) coupled to the stacked channels;
a gate metal (144 – par [0044] and metal gate electrode layer (par [0026]) wrapped around the stacked channels;
a plurality of inner spacers 126, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap 136 between the gate metal and the source/drain region,
wherein the source/drain region includes a curved surface (see rounded curved surface of 132 and sharped curve of 134) adjacent to the gaps.
Regarding claim 11, fig. 4D of Lin discloses a method, comprising:
forming a first channel (middle 106) of a transistor stacked above a second channel (bottom 106) of the transistor;
forming a source/drain region 139 (par [0047]) in contact with the first channel and the second channel;
forming a gate metal (144 – par [0044] and metal gate electrode layer (par [0026]) wrapped around the first channel and the second channel; and
forming an inner spacer 136/126 between the gate metal and the source/drain region and including a gap 136 and an inner spacer liner layer 141 between the gate metal,
wherein the inner spacer liner layer 141 includes a first curved end (inner curved surface) adjacent to the first channel and a second curved end (outer end curved surface) adjacent to the second channel,
wherein the gap is positioned between the source/drain region and the first curved end, wherein the gap is positioned between the second curved end and the source/drain region.
Regarding claim 2, fig. 4D of Lin discloses wherein each gap protrudes into the source/drain region.
Regarding claim 3, fig. 4D of Lin discloses wherein the source/drain has region has a sidewall that is concave where the sidewall abuts the gap of each inner spacer.
Regarding claim 4, fig. 4D of Lin discloses comprising: a source/drain contact 149 electrically connected to the source/drain region; a gate spacer 120 between the source/drain contact and the gate metal; and a dielectric structure (bottom surface of 120 a dielectric structure that directly contact top 106) above the highest channel 106, wherein a portion of the gate metal is above the dielectric structure, wherein a top of the gate spacer is higher than a top of the dielectric structure.
Regarding claim 6, fig. 4D of Lin discloses wherein the dielectric structure is in contact with the source/drain region and a gate dielectric layer above the highest channel.
Regarding claim 7, fig. 4D of Lin discloses wherein the transistor includes a gate dielectric layer 142 on the gate metal, wherein each inner spacer includes an inner spacer liner layer 126 on the gate dielectric between two adjacent channels and on the two adjacent channels, the gap being positioned between top, bottom, and side portions of the inner spacer liner layer.
Regarding claim 8, fig. 4D of Lin discloses wherein each inner spacer the inner spacer liner layer has a curved end adjacent to the source/drain region.
Regarding claim 12, fig. 2A of Lin discloses wherein forming the inner spacer includes: forming a sacrificial nanostructure 104 between the first channel and the second channel prior to forming the gate metal; forming a recess (fig. 2A – curve of 104 is a recess) between the first channel and the second channel by laterally recessing the sacrificial nanostructure with respect to the first channel and the second channel; and depositing the inner spacer liner layer 126 (fig. 2A) in the recess on a bottom of the first channel, on a top of the second channel, and on a lateral end of the sacrificial nanostructure 104.
Regarding claim 13, Lin discloses wherein forming the inner spacer 136 includes: filling the recess by depositing a dielectric material 126 (fig. 2A) on the inner spacer liner layer; and removing the dielectric material.
Regarding claim 14, figs. 4B-C of Lin discloses comprising forming the gap 136 by epitaxially growing the source/drain region from the first channel and the second channel in the presence of the inner spacer liner layer after removing the dielectric material.
Regarding claim 15, fig. 4D of Lin discloses wherein the source/drain region has a concave sidewall abutting the gap.
Regarding claim 16, fig. 4D of Lin discloses wherein forming the gate metal includes: removing the sacrificial nanostructure; and depositing the gate metal in place of the sacrificial nanostructure in a presence of the inner spacer liner layer.
Regarding clam 17, fig. 4D of Lin discloses forming a dielectric structure 145 above the first channel and in contact with the source/drain region.
Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mochizuki et al. 20180358435.
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Regarding claim 1, fig. 10 of Mochizuki discloses a device, comprising:
a transistor including:
a plurality of stacked channels 14A/B/C;
a source/drain region 30 coupled to the stacked channels;
a gate metal 38 (par [0066]) wrapped around the stacked channels;
a plurality of inner spacers 24P/32, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap 32 between the gate metal and the source/drain region,
wherein the source/drain region includes a curved surface (30 has a sharp concave curved surface) adjacent to the gaps.
Regarding claim 2, fig. 10 of Mochizuki discloses wherein each gap protrudes into the source/drain region.
Regarding claim 3, fig. 10 of Mochizuki discloses wherein the source/drain has region has a sidewall that is concave where the sidewall abuts the gap of each inner spacer.
Regarding claim 9, par [0037] of Mochizuki discloses wherein the inner spacer liner layer has a thickness between 0.5 nm and 3 nm (the gap G1 has a lateral thickness from 2 nm to 6 nm).
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. 20210020741.
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Regarding claim 18, fig. 12 of Wu discloses a device, comprising:
a transistor including:
a plurality of stacked channels;
a source/drain region 62 in contact with each of the stacked channels;
a gate metal 126 wrapped around the stacked channels and including an upper portion above a highest channel of the stacked channels;
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an inner spacer 102 including a gap 104’/104 above the highest channel and laterally between the upper portion of the gate metal and the source/drain region 62; and
a dielectric structure 72 above the gap 104’ (see B---B’) and in contact with the source/drain region 62.
Regarding claim 19, fig. 12 of Wu discloses wherein the inner spacer includes an inner spacer liner layer 102 lining the gap between the highest channel and the dielectric structure.
Regarding claim 20, fig. 12 of Wu discloses wherein the dielectric structure is positioned in contact with the inner spacer liner layer.
Regarding claim 21, Wu necessary discloses wherein the source/drain region has a curved sidewall adjacent to the gap (as surface non-uniformity inherently exist to some degree within production specification).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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