Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (20230005843).
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Regarding claim 1, Kang teaches a semiconductor chip, comprising:
a semiconductor substrate (fig. 13: 134a);
an insulation layer (fig. 13: 111) positioned on the semiconductor substrate and that comprises a plurality of via holes (please see fig. 13 above which shows 111 having multiple via holes); and
a bump (fig. 13: 115) positioned within the plurality of via holes and on the insulation layer (please see fig. 13 above),
wherein portions of the bump (portions that make up 115 are 114, 112b, 113 and 112a) positioned within the plurality of via holes are connected to each other (aforementioned portions of 115 can be seen within vias of 111).
Regarding claim 2, Kang teaches a semiconductor chip of claim 1, wherein, in a plan view, the bump covers a first surface of the insulation layer that surrounds surfaces of the plurality of via holes (please see fig. 13 shows this limitation).
Regarding claim 3, Kang teaches a semiconductor chip of claim 1, wherein a width of each of the plurality of via holes is 5 μm or more and 10 μm or less (par. 73 and 74).
Regarding claim 5, Kang teaches a semiconductor chip of claim 1, wherein: the number of via holes covered by the bump is four (115 is seen to have 4 portions); and the bump has a hexagonal planar shape that covers the four via holes (concerning the shape of the bump, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device).
Regarding claim 6, Kang teaches a semiconductor chip of claim 1, wherein: planar shapes of each of the plurality of via holes are circular (please see fig. 10B which shows this shape; further, concerning the shape of the via holes, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device).
Regarding claim 7, Kang teaches a semiconductor chip of claim 1, wherein the insulation layer contains a photosensitive polyimide (par. 36 teaches at least these materials).
Claims 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (20230005843).
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Regarding claim 8, Kang teaches a semiconductor chip, comprising:
a semiconductor substrate (fig. 13: 134a);
an insulation layer (fig. 13: 111) positioned on the semiconductor substrate and that comprises a plurality of via holes (please see fig. 13 above which shows 111 having multiple via holes); and
a bump (fig. 13: 115) positioned within the plurality of via holes and on portions of the insulation layer (please see fig. 13 above),
wherein the bump comprises:
a plurality of first portions (114, 113 and 112a) positioned within the plurality of via holes; and
a second portion (112b) that interconnects the plurality of first portions.
Regarding claim 9, Kang teaches a semiconductor chip of claim 8, wherein an upper surface of the second portion is flat (please see figure above which shows 112b having an upper flat surface).
Regarding claim 10, Kang teaches a semiconductor chip of claim 8, wherein the second portion covers the plurality of first portions and a portion of the insulation layer adjacent to the plurality of first portions (please see 112b which shows this limitation).
Regarding claim 11, Kang teaches a semiconductor chip of claim 8, wherein the plurality of first portions cover sidewalls and bottom surfaces of the plurality of via holes (please see 112b which shows this limitation).
Regarding claim 12, Kang teaches a semiconductor chip of claim 8, wherein upper surfaces of the plurality of first portions are in contact with a bottom surface of the second portion (as seen in fig 13, portions 114, 112b, 113 and 112a contact each other).
Regarding claim 13, Kang teaches a semiconductor chip of claim 8, wherein the plurality of first portions have a pillar shape in contact with inner walls of the plurality of via holes (as seen in fig 13, portions 114, 113 and 112 have this shape and are in contact with the via hole inner walls).
Claims 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (20230005843).
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Regarding claim 14, Kang teaches a semiconductor package, comprising:
a package substrate (fig. 13: 100) that comprises a trench (please see the trench wherein 134a resides);
a semiconductor chip (fig. 13: 134a) positioned within the trench of the package substrate;
a redistribution structure (fig. 13: 135) positioned on the semiconductor chip; and
a connection member (fig. 13: 250) connected to the redistribution structure,
wherein the semiconductor chip comprises:
a semiconductor substrate (fig. 13: 134a);
an insulation layer (fig. 13: 111) positioned on the semiconductor substrate and that comprises a plurality of via holes (please see fig. 13 above which shows 111 having multiple via holes); and
a bump (fig. 13: 115) positioned within the plurality of via holes and on portions of the insulation layer (please see fig. 13 above),
wherein the bump comprises:
a plurality of first portions (114, 113 and 112a) positioned within the plurality of via holes; and
a second portion (112b) that interconnects the plurality of first portions.
Regarding claim 15, Kang teaches a semiconductor package of claim 14, wherein the redistribution structure comprises: a plurality of wiring layers (133); an interlayer insulation layer (131) positioned between the plurality of wiring layers; a first redistribution via that penetrates the interlayer insulation layer and interconnects the plurality of wiring layers (please see above); and a second redistribution via that penetrates the interlayer insulation layer and interconnects the semiconductor chip and a lowermost wiring layer of the plurality of wiring layers (please see 135).
Regarding claim 16, Kang teaches a semiconductor package of claim 15, wherein the second redistribution via is in contact with the bump (please see the portions of the package being physically connected).
Regarding claim 17, Kang teaches a semiconductor package of claim 16, wherein a surface where the second redistribution via and the bump are in contact with each other is flat (please see fig. 13 show all layers being substantially flat).
Regarding claim 18, Kang teaches a semiconductor package of claim 16, wherein: the second redistribution via overlaps a bottom surface of the via hole of the insulation layer, in a plan view (please see fig. 13 which shows this limitation).
Regarding claim 19, Kang teaches a semiconductor package of claim 16, wherein: the second redistribution via overlaps a sidewall of the via hole of the insulation layer and a portion of the insulation layer adjacent to the sidewall, in a plan view (please see fig. 13 which shows these limitations).
Regarding claim 20, Kang teaches a semiconductor package of claim 16, wherein the second redistribution via overlaps a bottom surface of the via hole of the insulation layer, a sidewall of the via hole, and a portion of the insulation layer adjacent to the sidewall, in a plan view (please see fig. 13 which shows these limitations).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818