Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-3 and 5-13 have been considered but are moot because the new ground of rejection does not rely on any interpretation of the reference applied in the prior rejection of record. Please see new rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (20230005843).
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Regarding claim 1, Kang teaches a semiconductor chip, comprising:
a semiconductor substrate (fig. 13: 134a);
an insulation layer (fig. 13: 141) positioned on the semiconductor substrate and that comprises a plurality of via holes (please see fig. 13 above which shows 141 having multiple via holes); and
a bump (fig. 13: 114) positioned within the plurality of via holes and on the insulation layer (please see fig. 13 above),
wherein portions of the bump (portions that make up 114 can be seen in fig. 13) positioned within the plurality of via holes are in contact with the semiconductor substrate (as can be seen in fig.13, 114 is in contact with 134a) and are connected to each other (aforementioned portions of 115 can be seen within vias of 111).
Regarding claim 2, Kang teaches a semiconductor chip of claim 1, wherein, in a plan view, the bump covers a first surface of the insulation layer that surrounds surfaces of the plurality of via holes (please see fig. 13 shows this limitation).
Regarding claim 3, Kang teaches a semiconductor chip of claim 1, wherein a width of each of the plurality of via holes is 5 μm or more and 10 μm or less (par. 73 and 74).
Regarding claim 5, Kang teaches a semiconductor chip of claim 1, wherein: the number of via holes covered by the bump is four (114 is seen to have 4 portions); and the bump has a hexagonal planar shape that covers the four via holes (concerning the shape of the bump, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device).
Regarding claim 6, Kang teaches a semiconductor chip of claim 1, wherein: planar shapes of each of the plurality of via holes are circular (please see fig. 10B which shows this shape; further, concerning the shape of the via holes, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device).
Regarding claim 7, Kang teaches a semiconductor chip of claim 1, wherein the insulation layer contains a photosensitive polyimide (par. 61 teaches at least these materials).
Claims 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (20230005843).
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Regarding claim 8, Kang teaches a semiconductor chip, comprising:
a semiconductor substrate (fig. 13: 134a);
an insulation layer (fig. 13: 111b) positioned on the semiconductor substrate and that comprises a plurality of via holes (please see fig. 13 above which shows 111 having multiple via holes); and
a bump (fig. 13: 114+ 112b) positioned within the plurality of via holes and on portions of the insulation layer (please see fig. 13 above which shows 114 +112b being within the viaholes of 111b),
wherein the bump comprises:
a plurality of first portions (114) positioned within the plurality of via holes; and
a second portion (112b) that interconnects the plurality of first portions,
and wherein the plurality of via holes are spaced apart from each other in a direction parallel to a surface of the semiconductor substrate (please see that viaholes of 111b are spaced apart in a direction parallel to 134a).
Regarding claim 9, Kang teaches a semiconductor chip of claim 8, wherein an upper surface of the second portion is flat (please see figure above which shows 112b having an upper flat surface).
Regarding claim 10, Kang teaches a semiconductor chip of claim 8, wherein the second portion covers the plurality of first portions and a portion of the insulation layer adjacent to the plurality of first portions (please see 112b which shows this limitation).
Regarding claim 11, Kang teaches a semiconductor chip of claim 8, wherein the plurality of first portions cover sidewalls and bottom surfaces of the plurality of via holes (please see 112b which shows this limitation).
Regarding claim 12, Kang teaches a semiconductor chip of claim 8, wherein upper surfaces of the plurality of first portions are in contact with a bottom surface of the second portion (as seen in fig 13, portions 114 and 112b).
Regarding claim 13, Kang teaches a semiconductor chip of claim 8, wherein the plurality of first portions have a pillar shape in contact with inner walls of the plurality of via holes (as seen in fig 13, portions 114 and 112b have this shape and are in contact with the via hole inner walls).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to teach all structural limitations mentioned in newly amended claim 14..
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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