DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species B and species C, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 9, 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: semiconductor device with offset chip stacking.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-17 are rejected under U.S.C 102(a)(1) as being anticipated by OH (PG PUB No. US 20210257266 A1)
Regarding claim 13, Oh teaches a semiconductor device (¶0081, Fig 4/11) comprising:
a semiconductor substrate(¶0056, Fig 4/11:11);
a peripheral circuit structure (¶0082, Fig 11: 120) that includes peripheral circuits on the semiconductor substrate (11) and first bonding pads electrically connected to the peripheral circuits (¶0056, Fig 4/11: Pad1 electrically connects to 120);
a cell array structure ((¶0038, Fig 4/11: 110) that includes second bonding pads (Fig 4/11: Pad2) contacting the first bonding pads, wherein the cell array structure includes three-dimensionally integrated memory cells (110 includes 3-D integrated memory by vertically stacking);
a plurality of first vertical connection structures (¶0039, Fig 4/11: Composite of pad3, V1, pad2, 44a-41a, and the right most via of W3), electrically connected to the peripheral circuits (¶0038, fig 11: 120), wherein each of the plurality of first vertical connection structures includes a first upper pad (¶0039, fig 11: pad3), a first lower pad (¶0038, fig 11: pad2), and a first through via (¶0038, fig 11: V1) that is between the first upper pad and the first lower pad and electrically connects the first upper pad to the first lower pad (¶0039, Fig 11: pad3 and pad2 are coupled with V1 in between them); and
a plurality of second vertical connection structures (¶0042, fig 11: Composite of Tpad3, V2, Tpad2, and the left most via of W3) electrically insulated from the peripheral circuits (Fig 4/11: V2 is not connected to 120),
PNG
media_image1.png
476
771
media_image1.png
Greyscale
wherein each of the plurality of second vertical connection structures includes a second upper pad (¶0043, fig 4/11: Tpad3), a second lower pad (¶0043, fig 4/11:Tpad4), and a second through via (V2) that is between the second upper pad to the second lower pad electrically connects the second upper pad to the second lower pad (¶0042: V2 is coupled to tpad3 and Tpad4),
wherein the first and second upper pads are on an uppermost surface of the cell array structure (Fig 11, Tpad3 and Pad3 are at the top of the device region) w2, and
wherein the first and second lower pads are on a lowermost surface of the peripheral circuit structure (Fig 11, Tpad4 and pad4 are located on lowermost device region W3).
PNG
media_image2.png
526
728
media_image2.png
Greyscale
Regarding claim 14, Oh teaches the semiconductor device of claim 13, wherein each of the first (V1) and second through(v2) vias includes:
an upper via (V1 and V2 top half) in the cell array structure;
and a lower via (¶0066, fig 11: V3) in the peripheral circuit structure (w1),
wherein the lower via is electrically connected to at least one of the first bonding pads (¶0056, fig 11: V is coupled to pad1 and pad2), and
wherein the upper via is electrically connected to at least one of the second bonding pads (fig 11: V1 is coupled to pad2).
Regarding claim 15, Oh teaches the semiconductor device of claim 13, wherein the semiconductor substrate includes a device region (Oh, fig 11: right side of device) and a pad region (Oh, fig 11: left side of device) ,
the peripheral circuits (120) and the memory cells(110) are on the device region,
the plurality of first vertical connection structures (V2’) and the plurality of second vertical connection structures are on the pad region (V2), and
PNG
media_image3.png
476
771
media_image3.png
Greyscale
the plurality of first vertical connection structures are closer to the device region than the plurality of second vertical connection structures. (V2’ are on the pad region and are closer to the right side of the device than V2).
Regarding claim 16 Oh discloses the semiconductor device of claim 13, wherein the first through via is electrically connected through conductive lines (¶0056, fig 11: wiring lines 51a-53a) to the peripheral circuits (¶0056, fig 11: V1 is electrically connected by 51a-53a to W1)
Regarding claim 17, Oh discloses the semiconductor device of claim 13, wherein the cell array structure (¶0038, fig 11: 110) further includes:
a stack structure that includes a plurality of vertically stacked conductive patterns (¶0054, fig 4/11: electrode layers 20);
a plurality of vertical structures (¶0054, fig 4/11: CH) each of which is in the stack structure and includes a data storage layer (¶0054, memory cells can be configured where the word lines surround CH), and
a plurality of bit lines (¶0054, fig 4/11: BL) that traverse the stack structure and are electrically connected to the plurality of vertical structure (¶0054, fig 4/11: CH/BL channel layers with bit lines couple to them).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 6, 7, 8, 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pg Pub. No. US 20150108657 A1) in view of Kim (Pg Pub. US 20190221520 A1, hereinafter ‘Kim2’).
Regarding claim 1, Kim discloses a semiconductor package (Kim ¶0016, fig 2B: semiconductor device 200) comprising:
a package substrate (¶0026: 400); and
a first chip (¶0026:200b) and a second chip (¶0026:200a) that are stacked on the package substrate(fig 2B: 200a and 200b on 400),
wherein each of the first semiconductor chip, and the second semiconductor chip includes a plurality of first vertical connection structures(Kim ¶0030, fig2B: TSV’s 220c and 220g) and a plurality of second vertical connection structures(220b and 220f), (200a and 200b of Kim include 220c/220g and 220b/220f of Kim2) and
wherein the plurality of first vertical connection structures, of the second semiconductor chip overlap and are electrically connected with the plurality of second vertical connection structures of the first semiconductor chip , respectively (220c/220g of chip 200a overlap and electrically connect to 220b/220f of chip 200b).
Kim further teaches the package includes memory chips (¶0032).
Kim does not teach a plurality of first semiconductor chips are stacked vertically, and a plurality of second semiconductor chips are stacked vertically.
Kim2 teaches a chip stack that includes a plurality of chips 120 1-4 (¶0030)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first and second chips in Kim with a plurality of chips in Kim2 to increase memory capacity.
Regarding claim 2, Kim teaches the semiconductor package of claim 1, including a package substrate (Kim ¶0026, fig 2B: 400). Kim does not teach the semiconductor package further comprising a buffer chip on the package substrate,
wherein the plurality of second vertical connection structures of the plurality of first semiconductor chips electrically connect the buffer chip to the plurality of first vertical connection structures of the plurality of second semiconductor chips.
Kim2 teaches a buffer chip (Kim2, ¶0005-¶0007, fig 1: 110) on the package substrate (¶0022, fig 1:112) , wherein the plurality of second vertical connection structures (Kim2 ¶0022, fig. 1: 124 second via from the right) of the plurality of first semiconductor chips (¶0021, fig1:120-1) electrically connect the buffer chip to the plurality of first vertical connection structures (¶0022, fig 1: first 124 via from the right) of the plurality of second semiconductor chips (¶0021 fig. 1: 120-2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to further include the buffer chip of Kim2, to communicate with the controller, reduce parasitic capacitance improving signal integrity.
Regarding claim 4, Kim in view of Kim2 discloses the semiconductor package of claim 1, wherein
in each of the plurality of first semiconductor chips (Kim 200b) and the plurality of second semiconductor chips (Kim 200a), the plurality of first vertical connection structures (Kim 220c/220g) are arranged along a first direction, and the plurality of second vertical connection structures (220b/220g) are spaced apart in a second direction from the plurality of first vertical connection structures ( Kim Fig 2B: In stacks 200b and 200a, 220c/220g are arranged vertically apart from each other. In stacks 200b and 200a 220b/220f are spaced in horizontally from 220c/220g),
a sidewall of the first chip stack is spaced apart in the second direction from a sidewall of the second chip stack, and the sidewalls of the first and second chip stacks are parallel to the first direction. (Fig 2B: sidewall of 200b is spaced horizontally from sidewall of 200a).
PNG
media_image4.png
392
625
media_image4.png
Greyscale
Regarding claim 6, Kim in view of Kim2 discloses the semiconductor package of claim 1,
wherein sidewalls of the plurality of first semiconductor chips are vertically aligned with each other, and sidewalls of the plurality of second semiconductor chips are vertically aligned with each other, and
the sidewalls of the plurality of first semiconductor chips are misaligned with the sidewalls of the plurality of second semiconductor chips. (Kim2, fig 1: sidewalls of chips 120 1,2,3,and 4 are vertically aligned, and Kim, fig 2b: chip stack 200b is offset with chip stack 200a).
Regarding claim 7, Kim, and Kim2 discloses the semiconductor package of claim 1, wherein the plurality of second vertical connection structures (Kim, fig 2B: 220b/220e) of the plurality of second semiconductor chips (Kim 200a) are electrically floated (Kim, fig 2B: at least the bottom of through connection 220b/220e including element 300k is not connected to voltage or ground, meeting the broadest reasonable interpretation of ‘electrically floating’).
Regarding claim 8, Kim in view of Kim2 discloses the semiconductor package of claim 1,
wherein each of the plurality of first vertical connection structures includes a first upper pad (Kim2: 125), a first lower pad (Kim2: 115), and a first through via (Kim2 Fig 1: 124 on stack 120-1 ) that electrically connects the first upper pad to and the first lower pad, and
each of the plurality of second vertical connection structures (Kim2, fig 1: Chip stack 120-1 and second 124 from the right) includes a second upper pad (Kim2, fig 1:Chip stack 120-1 and second 125 from the right), a second lower pad (Kim2, fig 1:Chip stack 120-1 and second 115 from the right), and a second through via that electrically connects the second upper pad to the second lower pad. (Kim2 0004 fig 1: vertical row 1, 124 electrically connects upper pad 125 and lower pad 115, vertical row 2, 124 electrically connects 125 to 115)
PNG
media_image5.png
411
582
media_image5.png
Greyscale
Regarding claim 9, Kim in view of Kim2 disclosed the semiconductor package of claim 1, further comprising a plurality of connection bumps (Kim ¶0035, fig 1: 300a-300i), between the first chip stack and the second chip stack,
wherein the plurality of connection bumps are between the plurality of first vertical connection structures of a lowermost one of the plurality of second semiconductor chips and the plurality of second vertical connection structures of an uppermost one of the plurality of first semiconductor chips (Kim, 300d is between 200b and 200a, where 300d is between 220c and 220f).
Regarding claim 11 Kim in view of Kim2 discloses the semiconductor package of claim 1, comprising first and second chip stacks (Kim, 200a & 200b, as modified to include stacks 120 1-4 of Kim2). Kim in view of Kim2 further teaches additional levels if chips/chip stacks (Kim, fig. 2B: at least three levels 100a-100c).
Kim in view of Kim2 does not explicitly teach the package further comprising:
a third chip stack on the second chip stack ; and
a fourth chip stack on the third chip stack,
wherein the third chip stack includes a plurality of third semiconductor chips and the fourth chip stack includes a plurality of fourth semiconductor chips, the plurality of third semiconductor chips are stacked vertically, and the plurality of fourth semiconductor chips are stacked vertically,
wherein each of the plurality of third semiconductor chips and the plurality of fourth semiconductor chips includes a plurality of first vertical connection structures and a plurality of second vertical connection structures,
wherein each of the plurality of first semiconductor chips, the plurality of second semiconductor chips, the plurality of third semiconductor chips, and the plurality of fourth semiconductor chips further includes a plurality of third vertical connection structures and a plurality of fourth vertical connection structures,
wherein the plurality of first vertical connection structures of the plurality of third semiconductor chips overlap and are electrically connected with the plurality of second vertical connection structures of the plurality of second semiconductor chips, respectively, and
wherein the plurality of second vertical connection structures of the plurality of second semiconductor chips overlap and are electrically connected with the plurality of third vertical connection structures of the plurality of first semiconductor chips, respectively.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kim in view of Kim2 to include third and fourth chip stacks as claimed, as a means to add additional chip stacks and increase the memory storage capacity and chip efficiency.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, modifying Kim in view of Kim2 to further include third semiconductor chips and third vertical connection structures represent a mere duplication of the first and second semiconductor chips and vertical connection structures of Kim in view of Kim2.
Regarding claim 12, Kim in view of Kim2 teaches the semiconductor package of claim 11,
Kim in view of Kim2 does not explicitly teach wherein the plurality of first vertical connection structures of the plurality of fourth semiconductor chips, respectively, overlap and are electrically connected with the plurality of second vertical connection structures of the plurality of third semiconductor chips, respectively, the plurality of third vertical connection structures of the plurality of second semiconductor chips, and the plurality of fourth vertical connection structures of the plurality of first semiconductor chips.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kim in view of Kim2 to include third and fourth chip stacks as claimed, and the offset connections of vertical connection structures. More thoroughly, chip stack 1 and 2 are offset, the repeated offset stacking on chips 3 and 4 will remain consistent so that at least one vertical connections structure in each chip are connected.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, modifying Kim in view of Kim2 to further include fourth semiconductor chips and fourth vertical connection structures represent a mere duplication of the first and second semiconductor chips and vertical connection structures of Kim in view of Kim2.
Claim(s) 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kim2 and OH
Regarding claim 10, Kim in view of Kim2 discloses the semiconductor package of claim 1, wherein each of the plurality of first semiconductor chips and the plurality of second semiconductor chips includes:
a semiconductor substrate (Kim, fig. 2B: 400);
Kim in view of Kim2 does not disclose a peripheral circuit structure that includes peripheral circuits on the semiconductor substrate and first bonding pads electrically connected to the peripheral circuits; and
a cell array structure that includes second bonding pads contacting the first bonding pads, wherein the cell array structure includes three-dimensionally integrated memory cells, wherein the plurality of first vertical connection structures are electrically connected to the peripheral circuits,
and wherein the plurality of second vertical connection structures are electrically insulated from the peripheral circuits.
Oh, discloses a peripheral circuit structure(Oh ¶0038, Fig 1: W1) that includes peripheral circuits (Oh ¶0038, Fig 1: 120) on the semiconductor substrate (Oh ¶0056, Fig 1:11) and first bonding pads (Oh ¶0039, Fig 4: Pad1) electrically connected to the peripheral circuits; and
a cell array structure ((Oh ¶0038, Fig 11: 110) that includes second bonding pads contacting the first bonding pads (Oh ¶0039, Fig 4/11: Pad contacts pad 1), wherein the cell array structure includes three-dimensionally integrated memory cells (Oh ¶0038),
wherein the plurality of first vertical connection structures (Oh ¶0039, fig 11: V1), are electrically connected to the peripheral circuits and wherein the plurality of second vertical connection structures are electrically insulated from the peripheral circuits (OH fig 11: 120 on 11 and Pad1 electrically connects to 120, 110 includes pad2 contacting pad1, V1 is electrically connected to 120 and V2 is electrically insulated from 120).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to continue to stack the embodiment in Oh to make the plurality of chips in Kim2 to create a memory die stack, increasing memory capacity of the package. Also, including the addition of a peripheral circuit for controlling the operation of each memory cell array (Oh ¶0038). The second though via of Oh (Oh V2) does not touch the peripheral region (Oh 120), meeting the broadest reasonable interpretation of “electrically insulated”.
Regarding claim 18, Kim teaches a semiconductor package (Kim ¶0016 fig 2B:200) comprising:
a package substrate (400);
a first chip stack on the package substrate (Kim ¶0026 ,fig 2B: 200b);
a second chip stack on the first chip stack (Kim ¶0026 ,fig 2B: 200a); and
wherein the first chip stack (200b), the second chip stack (200a) the semiconductor chips are vertically stacked (Kim stack 200a vertically stacked on 200b),
wherein the plurality of first vertical connection structures (Kim fig 2B: 220c/220g) of the second semiconductor chip stack (Kim 200a) overlap and are electrically connected with the plurality of second vertical connection structures (Kim, fig 2B: 220b/220f) of the first semiconductor chip stack (Kim 200b)
Kim does not teach a plurality of chips in each chip stack, a buffer chip on a substrate, and a plurality of first vertical connection structures electrically connected to the buffer chip through the second vertical connection structures in the first chip stack. Kim 2 teaches a semiconductor package (Kim2 ¶0020, fig 1: 100) with a plurality of chips and vertical connections (Kim2, ¶0024, fig 1: 114), a buffer chip on the substrate (Kim2, ¶0022 fig 1: 112) (Kim2 ¶0007 fig 1: buffer chip on 112), and
includes a plurality of first semiconductor chips (Kim2 ¶0030, fig 1: 120 1-4) includes a plurality of second semiconductor chips (Kim2 ¶0030, fig 1: 120 1-4),
the plurality of first semiconductor chips (Kim2 120 1-4) are vertically stacked, and the plurality of second semiconductor chips (Kim2 120 1-4) are vertically stacked (Kim2 fig 1: chip stack 120 1-4 are stacked on top of each other),
wherein the plurality of first vertical connection structures (Kim2, fig 1:124 of chip 120-2) electrically connected to the buffer chip (Kim2 110) through the plurality of second vertical connection structures (Kim2, 124 of 120-1) of the first chip stack (Kim2 ¶0008, fig 1: 120-2 electrically connected to 110 through 124 of 120-1),
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Kim with the buffer chip of Kim2 to increase bandwidth and improve signal integrity.
Furthermore, configuring the semiconductor package of Kim with a plurality of chips in each chip stack of Kim2 to increase memory capacity.
In addition, configuring the semiconductor package of Kim with a plurality of first vertical connection structures electrically connected to the buffer chip through the second vertical connection structures in the first chip stack to shorten the electrical path, increase density and increase reliability (Kim ¶0003).
Kim in view of Kim2 fails to teach, wherein each of the plurality of first semiconductor chips and the plurality of second semiconductor chips includes:
a semiconductor substrate; a peripheral circuit structure that includes peripheral circuits on the semiconductor substrate and first bonding pads electrically connected to the peripheral circuits;
a cell array structure that includes second bonding pad contacting the first bonding pads, wherein the cell array structure includes three-dimensionally integrated memory cells; a plurality of first vertical connection structures electrically connected to the peripheral circuits; and a plurality of second vertical connection structures electrically insulated from the peripheral circuits .
Oh, teaches wherein each of the plurality of first semiconductor chips of and the plurality of second semiconductor chips includes:
a semiconductor substrate (Oh, fig 4/11: 10);
a peripheral circuit structure (Oh, fig 4/11: W1) that includes peripheral circuits (Oh, fig 4/11: 120) on the semiconductor substrate (Oh, fig 4/11: 120 on 11) and first bonding pads electrically connected to the peripheral circuits (Oh ¶0039, Pad1 is coupled to W1);
a cell array structure (Oh, fig 4/11: 110) that includes second bonding pad contacting the first bonding pads (Oh ¶0040, fig 4/11: pad2 is coupled to pad1), wherein the cell array structure includes three-dimensionally integrated memory cells (Oh, fig 4/11 : 110 is inherently three-dimensional due to it being vertically stacked);
a plurality of first vertical connection structures (Oh V1) electrically connected to the peripheral circuits (Oh ¶0039, fig 4/11: V1 connected to 120 through pad1); and
a plurality of second vertical connection structures electrically insulated from the peripheral circuits (V2 not connected to 120),
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to continue to configure the chip stacking of Kim with the plurality of chips and vertical connections of Kim2 with the device of Oh to increase memory data storage as well as to compensate for an increase of a thickness of the semiconductor package due to vertical stacking (Choi Pg Pub No. US 20210217700).
Regarding claim 19, Kim in view of Kim2 and Oh teaches the semiconductor package of claim 18, wherein the plurality of second vertical connection structures of the plurality of second semiconductor chips are electrically floated (Kim, fig 2B: at least the bottom of through connection 220b/220e including element 300k is not connected to voltage or ground, meeting the broadest reasonable interpretation of ‘electrically floating’).
PNG
media_image6.png
410
694
media_image6.png
Greyscale
Regarding claim 20, Kim, in view of Kim2 and Oh teach the semiconductor package of claim 18, wherein
sidewalls of the plurality of first semiconductor chips (Kim 220b) are vertically aligned with each other, and sidewalls of the plurality of second semiconductor chips (Kim 220a) are vertically aligned with each other, and
the sidewalls of the plurality of first semiconductor chips are misaligned with the sidewalls of the plurality of second semiconductor chips (220b and 200a are stacked vertically, the right sidewalls of the chip stacks are not lined up).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, The semiconductor package of claim 1, wherein, in each of the plurality of first semiconductor chips and the plurality of second semiconductor chips, the plurality of first vertical connection structures are electrically connected to an internal circuit of each of the plurality of first semiconductor chips and the plurality of second semiconductor chips, and the plurality of second vertical connection structures are electrically insulated from the internal circuit.
Kim, Kim2, and Oh do not teach the first vertical connection structures are connected to an internal circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Woon et. Al. (Pub. No. KR 20210034784 A, cited on applicant’s IDS) teaches the application of the buffer chip (Page 15, Fig 2: 160) on the substrate to communicate with the controller, reduce parasitic capacitance improving signal integrity.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LYTESHIA M PRICE/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights