DETAILED ACTION
Claims 1-2 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Are the claims even related to mask information? While the parent application focused on the mask embodiment, this application is directed to register data. The examiner recommends a title of --Parallelizing Instructions Upon Observing Non-Operating State of Processing Apparatuses based on Transferred Register Data--.
The abstract of the disclosure is objected to because of the following minor informalities:
First, applicant did not appear to amend the abstract from June 4, 2024. Thus, markings are not correct and not in compliance with 37 CFR 1.121.
Starting with the abstract filed on June 4, 2024:
In line 3, insert --decoded-- after “the” and delete “which are decoded”.
In line 3, replace “and” with a semicolon.
In line 5, insert a semicolon after “processed”.
In line 5, replace “observe” with --observes--.
In the 2nd to last line, there is a lack of basis for “the instructions”. Amend to clarify which instructions applicant is referring to.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
While there is no formal objection to the drawings, the examiner recommends that applicant try to improve the quality of the drawings, which are fuzzy, to improve print quality. Applicant should use smooth, solid, black lines.
Claim Objections
The claim amendments are not in compliance with 37 CFR 1.121, as applicant does not appear to have amended the most recent version of the claims submitted on June 4, 2024.
Claim 1 is objected to because of the following informalities:
In line 9, delete the comma after “wherein”.
Replace “steam” with --stream--.
In the last line, replace “apparatus” with --apparatuses--.
Claim 2 is objected to for similar reasoning as claim 1, and further because:
In line 4, replace “output” with --outputting--.
Lines 8-9 are grammatically incorrect and must be reworded.
Replace “steam” with --stream--.
In the last line, replace “apparatus” with --apparatuses--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 1, “data used by the plurality of sub-computation processing apparatuses”, “subset of the plurality of sub-computation processing apparatuses does not execute at least one instruction”, and “concurrent execution by the plurality of sub-computation processing apparatus [sic]”. From paragraph 85, the apparatuses are interpreted as arithmetic logic units (ALUs). If applicant does not wish to be so limited, applicant may claim circuits instead of apparatuses.
In claim 2, “subset of the plurality of sub-computation processing apparatuses does not execute at least one instruction”, and “concurrent execution by the plurality of sub-computation processing apparatus [sic]”. These apparatuses are similarly interpreted as ALUs.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
At least one claim is identified as including non-limiting contingent limitations.
“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 2, the parallelizing and outputting in the last paragraph are not required to occur if it is not observed that a subset of the plurality of sub-computation processing apparatuses does not execute at least one instruction. The examiner again recommends claiming a positively recited step of --observing that a subset…does not execute at least one instruction; and--. This can then be followed by --in response to observing that the subset…does not execute at least one instruction, parallelizing…--.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claims 1-2, applicant claims a register to hold data to be used by the plurality of sub-computation processing apparatuses. The examiner has been unable to find original support for a single register holding data for (and transferring data to) multiple apparatuses/ALUs. From FIG.8 and paragraphs 84 and 86, applicant has a register file 60 holding data to be used by multiple apparatuses, but not necessarily a single register. Thus, applicant’s claims include new matter, and the examiner recommends claiming a register file, not a singular register.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 1, “the data transferred from the register…”. Applicant previously sets forth data held in a register, but not data transferred from the register to the plurality of sub-computation processing apparatuses. It is not clear that these data are the same data.
In claim 2, “the data transferred from the register…” for similar reasoning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 2 is firstly rejected under 35 U.S.C. 102(a)(1) as being anticipated by Atoofian et al., “Improving energy-efficiency in high-performance processors by bypassing trivial instructions”.
Referring to claim 2, Atoofian has taught a method of processing in a computation processing apparatus, the method comprising:
decoding instructions from an instruction stream (Fig.5a, “DECODE”, which decodes fetched instructions);
output the decoded instructions (the purpose of decoding is to output decoded instructions to control other processing circuitry to execute operations associated with the instructions);
executing the decoded instructions (the last paragraph before section 4 mentions
“execution units”, which execute decoded instructions issued from the ISSUE stage in the pipeline of FIG.5a);
operating as a plurality of sub-computation processing apparatuses in accordance
with a bit width of data to be processed (again, plural “execution units” will operate as such apparatuses on a bit width of data that they are designed to process);
holding data to be used in the a plurality of sub-computation processing
apparatuses to a register (from FIG.5b, a register in a register file holds operand data, that when read, is output and transferred to circuitry to execute an operation);
observing an operation state of the computation processing apparatus based on the
data transferred from the register to the plurality of sub-computation processing apparatuses (see the abstract and section 1, which discuss observing operand data to bypass trivial operations to reduce energy consumption. This involves observing a type of instruction to perform and a value of at least one operand. For instance, see Table 1 on p.2. When a multiplication instruction is to be executed and one of its operands is 0, the system does not need to perform the multiplication because the answer is automatically 0. FIG.5 shows that operands that are transferred/read from registers on their way to execute apparatuses are observed to determine if the value indicates a trivial operation, and, if so, the operation can be bypassed);
(the struck-through language is not required due to contingency).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Fung et al., “Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow” (as cited by applicant), in view of Atoofian.
Referring to claim 1, Fung has taught a computation processing apparatus (Figures 2-3) comprising:
a processor (Figure 2, at least one shader core) coupled to a memory (Figure 2, GDDR3) and configured to:
decode instructions from an instruction stream (Figures 2-3, “Decode”);
output the decoded instructions (from Figures 2-3, see the arrows indicating flow of decoded instructions from the decode stage to subsequent logic);
execute the decoded instructions (from Figures 2-3, decoded instructions are executed by the Pipelines/ALUs);
operate as a plurality of sub-computation processing apparatuses (note the multiple pipelines in Figure 2. These include ALUs as shown in Figure 3) in accordance with a bit width of data to be processed (see Figure 9. When all threads execute the same code, a maximum bit width is to be collectively processed in all of the pipelines. However, when threads diverge, a smaller bit width is to be processed by fewer pipelines);
wherein, the computation processing apparatus further comprises a register configured to hold data to be used by the plurality of sub-computation processing apparatuses (Figure 3 shows a register being read. A register is storage that holds data to be used by the group of ALUs), and
in response to observing that a subset of the plurality of sub-computation processing apparatuses does not execute at least one instruction, the processor parallelizes a first decoded instruction from the instruction steam with at least one subsequent decoded instruction from the instruction stream and outputs the parallelized instructions for concurrent execution by the plurality of sub-computation processing apparatus (see Figure 9. It is observed that threads diverge in warp 0 (W0). That is, two threads go to code A and the other two threads go to code B. The system observes this, i.e., that two of the pipelines do not execute at least one instruction of code A and, thus, the processor parallelizes the two threads of W0 that do execute code A with two threads of warp 1 (W1) that also execute code A. The parallelization is shown as warp 2 (W2)). Note that each arrow represents an instruction, so the top arrow in W2 would be a first instruction, and the bottom arrow in W2 would be a subsequent decoded instruction, where the instruction is subsequently decoded with respect to the code that precedes the divergent point in Figure 9 (note the execution flow leading into the divergent point, meaning instructions are decoded/executed before the divergent point)).
Fung has not taught wherein the processer observes the operation state of the computation processing apparatus based on the data transferred from the register to the plurality of sub-computation processing apparatuses. However, Atoofian has taught bypassing trivial operations to reduce energy consumption (abstract and section 1). This involves observing a type of instruction to perform and a value of at least one operand. For instance, see Table 1 on p.2. When a multiplication instruction is to be executed and one of its operands is 0, then the system does not need to perform the multiplication because the answer is automatically 0. FIGs.5b-c, for instance, show that operand values that are transferred/read from registers on their way to execution apparatuses are observed to determine if the values indicate a trivial operation, and, if so, the operation can be bypassed. As a result, to save energy and time by not performing operations whose result can be deduced without performing the operations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fung such that the processer observes the operation state of the computation processing apparatus based on the data transferred from the register to the plurality of sub-computation processing apparatuses. In the example of multiplication, when it is observed that a register is transferring a “0” operand to a processing apparatus, an operation will be skipped to save power.
Claim 2 is secondly rejected for similar reasoning as claim 1.
Response to Arguments
Regarding the 102 rejection of method claim 2, applicant argues that Atoofian has not taught the last paragraph of the claim. However, this paragraph is a contingent limitation which need not be performed. Where Atoofian does not make the observation of the last paragraph, the claimed parallelizing and outputting need not be disclosed to anticipate the claim.
On page 9 of applicant’s response, applicant argues that Fung and the claims are fundamentally different in every aspect.
The examiner respectfully disagrees for reasons set forth in the updated rejection above. The claim is too broad to preclude rejection.
On page 9 of applicant’s response, applicant argues that the combination would not lead to the claimed parallelizing.
The examiner notes that Fung alone has taught the claimed parallelizing. Atoofian is not relied on for the parallelizing. The examiner notes that the observation in claim 1, lines 12-14, is not even the same as (or necessarily tied to) the observation in claim 1, lines 14-16. This is why two different references are combined in the rejection of claim 1, one for each separate observation.
On pages 9-10 of applicant’s response, applicant argues that the technical effect of energy reduction is different from the claims invention that realized an increase in throughput and that there is no motivation to combine.
The examiner respectfully disagrees that there is no motivation. Actions to reduce energy consumption are not in conflict with actions to increase throughput. One would expect to try both to improve multiple aspects of the system. In other words, it is obvious to add the bypassing/skipping of Atoofian to Fung to additionally save energy when trivial operations are detected. Fung can continue to try to improve throughput where threads diverge.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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