Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-7, 9, 11-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20220384609A1; Lin et al.; (hereinafter “Lin”) in view of US20220051939A1; Sheng-hui Yang; (hereinafter “Yang”).
Regarding Claim 1 (currently amended), Lin teaches a method for forming a semiconductor device structure (Figure 19), comprising:
forming a metal gate stack (#1602) wrapped around a plurality of semiconductor nanostructures (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606), the gate electrode has a work function layer and a conductive filling, the work function layer is between the conductive filling and the gate dielectric layer ([0040], #1606 comprises work function layer and fill material), and the semiconductor nanostructures are adjacent to an epitaxial structure (#1202, [0034]);
forming a protective structure (#1302/#1304) over the epitaxial structure (#1202), wherein the protective structure laterally surrounds the protruding portion of the work function layer (#1302/#1304 surrounds #1606); and
forming a conductive contact (#1904) electrically connected to the epitaxial structure (#1202, [0034]) and penetrating through the protective structure (#1302/#1304).
Lin does not explicitly teach recessing the gate dielectric layer, wherein a protruding portion of the work function layer protrudes from a top surface of the gate dielectric layer after the gate dielectric layer is recessed.
However, Yang teaches a method for forming a semiconductor structure ([0001]) comprising recessing the gate dielectric layer (#18R, Figure 4, [0077-0078], recessed gate dielectric), wherein a protruding portion of the work function layer protrudes from a top surface of the gate dielectric layer after the gate dielectric layer is recessed (conductive materials of gate conductor and work-function metal #20, [0071], protrudes from top surface of recessed gate dielectric #18R).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Yang in order to provide a device geometry with reduced gate resistance according to Yang, [0081].
Regarding Claim 2, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 1, wherein Lin further teaches:
forming a dielectric layer (#1702, Figure 17) over the metal gate stack (#1602), the protective structure (#1302/#1304), and the epitaxial structure (#1202);
forming a contact opening (#1802, Figure 18) in the dielectric layer (#1702);
forming a protective layer (#1302/#1304) over sidewalls of the contact opening (#1802);
partially removing the protective structure to expose the epitaxial structure after the protective layer is formed (#1302-#1304 are partially removed to expose epitaxial drain #1202); and
forming the conductive contact (#1904, Figure 19) such that at least a portion of the conductive contact is in the contact opening (#1802).
Regarding Claim 3, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 2, wherein Lin further teaches deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer (Figure 18-19, [0049], opening #1802 extends for formation of silicide features #1902).
Regarding Claim 5, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 3, wherein Lin further teaches forming a metal-semiconductor compound element (#1902, Figure 19, [0049]) on the epitaxial structure (#1202), wherein the metal-semiconductor compound element (#1902) is between the conductive contact (#1904) and the epitaxial structure (#1202).
Regarding Claim 6, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 5, wherein Lin further teaches the metal-semiconductor compound element is separated from the protective layer by the protective structure (Figure 19, silicide feature #1902 is separated from dielectric layer #1304 by dielectric layer #1302).
Regarding Claim 7, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 1, wherein Lin further teaches:
forming a fin structure (#402, Figure 7) over a substrate (#300), wherein the fin structure has a plurality of semiconductor layers (#306) and a plurality of sacrificial layers (#304) laid out in an alternating manner;
forming a dummy gate stack (#612) extending across the fin structure (402);
partially removing the fin structure (Figure 9) to form a recess (#902) exposing side surfaces of the semiconductor layers (#306) and the sacrificial layers (#304);
forming the epitaxial structure (#1202, Figure 12) in the recess;
forming a second dielectric layer (#1302/#1304, Figure 13) laterally surrounding the epitaxial structure (#1202) and the dummy gate stack (#612); and
removing the dummy gate stack (#612, Figure 14) and the sacrificial layers (#304), wherein remaining portions of the semiconductor layers form the semiconductor nanostructures (#306).
Regarding Claim 9, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 1.
Lin does not teach the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer.
However, Yang teaches a protective structure is formed to be in direct contact with gate electrode and gate dielectric layer (Figure 7, dielectric cap #22 directly contacts gate electrode #20S and gate dielectric #18S).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Yang in order to protect the gate during contact etch while improving fill margin according to Yang, [0087-0088].
Regarding Claim 11 (currently amended), Lin teaches a method for forming a semiconductor device structure (Figure 19 of Lin annotated), comprising:
forming a metal gate stack (#1602) extending across a semiconductor nanostructure (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606), the gate dielectric layer (#1604) has a first sidewall (#SW1) and a second sidewall (#SW2), the first sidewall (#SW1) is between the second sidewall (#SW2) and the gate electrode (#1606), and the semiconductor nanostructure (#306) is electrically connected to an epitaxial structure (#1202, [0034]), wherein a dielectric layer (#702) laterally surround the metal gate stack (#1606) and cover the epitaxial structure (#1202);
forming a protective structure (#1302/#1304) laterally surrounding the sidewall of the gate electrode (#1606); and
forming a conductive contact (#1904) electrically connected to the epitaxial structure (#1202) and penetrating through the protective structure (#1302/#1304).
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Lin does not explicitly teach partially removing the dielectric layer to expose the second sidewall of the gate dielectric layer; removing the gate dielectric layer so that a sidewall of the gate electrode previously covered by the gate dielectric layer is exposed;
However, Yang teaches a method for forming a semiconductor structure ([0014]) comprising partially removing the dielectric layer to expose a second sidewall of gate dielectric layer (Figure 3, recessed dielectric layer #14R exposes outer sidewall of gate dielectric #18); removing the gate dielectric layer so that a sidewall of the gate electrode previously covered by the gate dielectric layer is exposed (Figure 4, [0077-0078], recessed gate dielectric #18R exposes the sidewall of gate conductor #20).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Yang in order to provide a device geometry with reduced gate resistance according to Yang, [0081].
Regarding Claim 12 (currently amended), Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches:
forming a second dielectric layer (#1702, Figure 17) over the metal gate stack (#1602), the protective structure (#1302/#1304), and the epitaxial structure (#1202);
partially removing the second dielectric layer (#1702, Figure 18) to form an opening (#1802) exposing the protective structure (#1302/#1304);
forming a protective layer (#1302/#1304) over sidewalls and a bottom of the opening (#1802);
partially removing the protective layer and the protective structure to expose the epitaxial structure (#1302-#1304 are partially removed to expose epitaxial drain #1202; and
forming the conductive contact (#1904, Figure 19) electrically connected to the epitaxial structure (#1202).
Regarding Claim 13, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 12, wherein Lin further teaches partially removing the epitaxial structure after the epitaxial structure is exposed and before the conductive contact is formed (Figure 18-19, [0049], opening #1802 extends for formation of silicide features #1902 before forming drain contact #1904).
Regarding Claim 14, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches forming a metal-semiconductor compound element (#1902, Figure 19, [0049]) on the epitaxial structure (#1202) before the conductive contact (#1904) is formed, wherein the metal-semiconductor compound element (#1902) is between the conductive contact (#1904) and the epitaxial structure (#1202).
Regarding Claim 15, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches the protective structure (#1302/#1304, Figure 19) is formed to be in direct contact with the epitaxial structure (#1202).
Lin does not teach the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer.
However, Yang teaches a protective structure is formed to be in direct contact with gate electrode and gate dielectric layer (Figure 7, dielectric cap #22 directly contacts gate electrode #20S and gate dielectric #18S).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Yang in order to protect the gate during contact etch while improving fill margin according to Yang, [0087-0088].
Regarding Claim 16 (currently amended), Lin teaches a semiconductor device structure (Figure 19), comprising:
an epitaxial structure (#1202, [0034]);
a semiconductor nanostructure (#306) electrically connected to the epitaxial structure (#1202);
a metal gate stack (#1602) extending across the semiconductor nanostructure (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606); and
a protective structure (layers #702-#1304, dielectric materials electrically isolate gate electrode from adjacent conductive structures) over the metal gate stack (#1602) and the epitaxial structure (#1202), wherein a bottom surface of the protective structure is vertically located between a top of the epitaxial structure and a bottom of the epitaxial structure (bottom of layer #702 is between top and bottom surface of epitaxial feature #1202).
Lin does not explicitly teach a topmost surface of the gate dielectric layer is between a top surface of the protective structure and a bottom surface of the protective structure, and the topmost surface of the gate dielectric layer is closer to the semiconductor nanostructure than a top of the metal gate stack.
However, Yang teaches a semiconductor device ([0001], Figure 16) comprising a topmost surface of the gate dielectric layer (#18S, gate dielectric) is between a top surface of a protective structure and a bottom surface of the protective structure (#18S is between the top and bottom surfaces of insulating layers #16/#22/#40), and the topmost surface of the gate dielectric layer is closer to semiconductor nanostructure than a top of the metal gate stack (topmost of gate dielectric #18S is closer to semiconductor nanowires #10, [0065], than a top of gate conductor #20S).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Yang in order to provide a device geometry with reduced gate resistance according to Yang, [0081].
Regarding Claim 17, Lin in view of Yang teaches the semiconductor device structure as described in claim 16, wherein Lin further teaches a conductive contact (#1904, Figure 19) electrically connected to the epitaxial structure (#1202), wherein the conductive contact penetrates through the protective structure (#1302/#1304).
Regarding Claim 20 (currently amended), Lin in view of Yang teaches the semiconductor device structure as described in claim 11, wherein Lin further teaches a metal-semiconductor compound element (#1902, Figure 19, [0049]) embedded in the epitaxial structure (#1202).
Claims 4, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yang, and further in view of US20200176597A1; Vellianitis et al.; (hereinafter “Vellianitis”).
Regarding Claim 4, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 3.
Lin in view of Yang do not explicitly teach the contact opening extends downwards across a top of the semiconductor nanostructures after the deepening of the contact opening.
However, Vellianitis teaches a manufacturing process of a gate-all-around FET device ([0034]), comprising the contact opening extends downwards across a top of the semiconductor nanostructures after the deepening of the contact opening (Figure 20B of Vellianitis, conductive contact layer #75 extends across the nanostructures).
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It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Yang with the teaching of Vellianitis, as it would be a simple substitution of one known element (contact features of Lin) for another (contact layer of Vellianitis) to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 10, Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 1.
Lin in view of Yang do not teach forming a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure.
However, Vellianitis teaches forming a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure (Figure 20B, a portion of ILD layer #50 extends across gate stack #82-86).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Yang with the teaching of Vellianitis by known methods to yield predictable results (implementation of a dielectric layer to insulate the gate structures). See MPEP 2143(I)(A).
Regarding Claim 19, Lin in view of Yang teaches the semiconductor device structure as described in claim 17.
Lin in view of Yang do not teach a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure.
However, Vellianitis teaches a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure (Figure 20B, a portion of ILD layer #50 extends across gate stack #82-86).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Yang with the teaching of Vellianitis by known methods to yield predictable results (implementation of a dielectric layer for insulating the gate structures). See MPEP 2143(I)(A).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yang, and further in view of US20190333812A1; Seong et al.; (hereinafter “Seong”).
Regarding Claim 8 (currently amended), Lin in view of Yang teaches the method for forming a semiconductor device structure as described in claim 7, wherein Lin further teaches:
forming gate spacers (#702, Figure 7 of Lin) over sidewalls of the dummy gate stack (#612) before the epitaxial structure is formed (Figure 12 of Lin); and
partially removing the gate spacers such that a top and a sidewall of the gate dielectric are exposed after the formation of the metal gate stack and before the recessing of the gate dielectric layer, wherein the gate dielectric layer is partially exposed after the partial removal of the gate spacers and the second dielectric layer (see rejection of claim 1, Yang, [0077-0078], Figures 3-4, gate spacer #14R is recessed after formation of gate stack #200 exposing top and sidewall of gate dielectric #18 and before subsequent recess of the gate dielectric).
Lin in view of Yang does not explicitly teach partially removing the second dielectric layer.
However, Seong teaches a method for fabricating a semiconductor device ([0119]), comprising partially removing a second dielectric layer (Figures 21-23, etch stop layer #162 is partially removed along with gate spacer #140 to expose sidewall of gate dielectric #120).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Yang with the teaching of Seong that provide fill margin to be implemented with additional etch stop layer that prevent short-circuit between gate electrode and source/drain contact according to Seong, [0072].
Regarding Claim 18, Lin in view of Yang teaches the semiconductor device structure as described in claim 17, wherein Lin further teaches a dielectric layer (#1702, Figure 19) laterally surrounding an upper portion of the conductive contact (#1904).
Lin in view of Yang does not explicitly teach a protective layer between the conductive contact and the dielectric layer, wherein the protective layer is separated from the epitaxial structure by the protective structure.
However, Seong teaches a protective layer (#175, Figure 13, [0107]) between a conductive contact (#190, contact) and a dielectric layer (#280, ILD layer), wherein the protective layer (#175) is separated from the epitaxial structure (#150, epitaxial source/drain) by the protective structure (#160, etch stop layer).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Yang with the teaching of Seong in order to efficiently reduce parasitic capacitance or leakage current between the gate electrode and the contact layer according to Seong, [0107].
Response to Amendments/Arguments
Applicant's amendments to claims 1, 11 and 16 and corresponding arguments, pages 12-16 of the remarks, filed 08/05/2026, with respect to the 35 U.S.C 103 rejection of the claims as unpatentable over Lin in view of Chang have been fully considered and are found persuasive. Accordingly, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Lin in view of Yang. Yang has been introduced in view of the amendments to claims 1, 11 and 16 (see 35 U.S.C. 103 rejections of amended claims 1, 11 and 16 above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20250113577A1 – Figures 1A-J and 3, [0049-0051], high-k dielectric layer is partially removed at various levels and exposes gate electrode which improve device’s effective capacitance.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
