CTNF 18/411,230 CTNF 101954 DETAILED ACTION This Office Action is in response to Application filed on January 12, 2024. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicants’ election without traverse of Group I drawn to a method for forming a trench bottom protection region in a metal-oxide semiconductor field-effect transistor (MOSFET) device as recited in claim 1 and drawn to the embodiments shown in Fig. 3D, claims 1-18, in the reply filed on May 27, 2026 is acknowledged. 08-25 AIA Applicant's election with traverse of the species restriction in the reply filed on May 27, 2026 is acknowledged. The traversal is on the ground(s) that the Examiner has not shown a serious burden to examine all the alleged species together . This is not found persuasive because Applicants do not provide any substantiating evidence that there would not be a serious search and examination burden to examine all the claims directed to all the species, and rather, Applicants do not provide any substantiating evidence that all the species are obvious variants from each other as stated in the Restriction Requirement mailed April 7, 2026 . The requirement is still deemed proper and is therefore made FINAL. Drawings The drawings are objected to under 37 CFR 1.83(a) because of the following reasons: The structure of the claimed “MOSFET device” is not shown in Figs. 3A-3C, see for example, claim 2 where Applicants claim that the claimed channeling implant process is performed toward the MOSFET device rather than an intermediate device structure on the way toward forming the claimed MOSFET device. The structure of the claimed “semiconductor epitaxial layer” shown in Fig. 3A is different from the structure of the claimed “semiconductor epitaxial layer” shown in Figs. 3B-C, while Applicants use the phrase “the semiconductor epitaxial layer” on line 13 of claim 1. The structure of the claimed “implant angle” shown in Fig. 3C is not oblique, although Applicants claim an angle which is not directly perpendicular to the device surface in claims 4 and 5. 06-22-01 Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 12 are rendered as indefinite because they recite the term “the semiconductor epitaxial layer” which has two different structures in the method shown by Figs. 3A-3D. The semiconductor epitaxial layer (element 310) shown in Fig. 3A has no trenches, and the semiconductor epitaxial layer (element 310) shown in Figs. 3B-3D has trenches. Because these elements have different structures, they need to be referred to using different terms and clarified in the claims instead of “a semiconductor epitaxial layer” and “the semiconductor epitaxial layer”. There is a lack of antecedent basis for the limitation “the semiconductor epitaxial layer” (element 310) with trenches shown in Figs. 3B-3D. Claims 1, 2, and 4 are rendered as indefinite because they recite the term “channeling implant process”. It is unclear what percentage of the shielding dopant is implanted by channeling. Are all of the shielding dopant atoms implanted via channeling in the interstitials of the crystal structure or are any implanted by substitution? What is the semiconductor epitaxial layer material, crystal structure and surface orientation? For purposes of examination, the term “channeling implant process” is interpreted by the Examiner as “ion implantation process”. In other words, claim 1 does not particularly point out and distinctly define the metes and bounds of the claimed subject matter, because Applicants do not specifically claim the ratio of the implanted shielding dopants that undergo the channeling, the angle of incidence of the implanted ions for the channeling, the material composition and surface orientation of the semiconductor region into which ions are implanted, the ion energy of the shieling dopant, temperature of the semiconductor region for the channeling implant process that is associated with lattice vibrations of the lattice atoms, which will prevent or deter a channeling process, etc., none of which Applicants specifically claim. Applicants are reminded that an implanted ion can undergo a channeling randomly or stochastically even if the implanted ion has not been implanted at an angle recited in claim 5, because the implanted ions would have a certain distribution of their energies and a certain distribution of their angles of incidence, i.e. not all the implanted ions have the same energy and impinge in the exactly the same direction, and a random implanted ion can undergo a channeling due to interaction with other implanted ions and/or vibration of lattice atoms, allowing a deep penetration of the implanted ion, especially when Applicants do not specifically claim how deep the ions should penetrate to be referred to have undergone a channeling implantation process. Claims 1, 2, and 4 are rendered as indefinite because they recite the term “MOSFET device”, which is not shown in Figs. 3A-3C. The intermediate structures shown in Figs. 3A-3C are not MOSFET devices because they do not contain a source, drain or gate electrode that is covered by an insulating material. For purposes of examination, the term “MOSFET device” is interpreted by the Examiner as “semiconductor device”. Claims 16 and 18 are rendered as indefinite because they recite the term “intentionally damaged”. It is unclear what the degree of damage which is being inflicted onto the lattice structures of the semiconductor source region and the body contact region. Claims 2-18 depend on claim 1, and therefore, claims 2-18 are also indefinite. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-2, 4, and 6-18, as best understood, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ebiike et al. (US 20190348524 A1) hereinafter referred to as “Ebiike” . Regarding claim 1, as best understood, Ebiike discloses a method for forming a trench bottom protective region in a metal-oxide-semiconductor field-effect transistor (MOSFET) device (Figs. 2-4, Figs. 6-7), the method comprising: forming at a top surface of a semiconductor epitaxial layer (element 10) ([0035]) and within the semiconductor epitaxial layer (element 10) a semiconductor body region (element 13) (Figs. 2 and 3, paragraphs [0048-0049]); wherein the semiconductor epitaxial layer (elements 10 and 12) comprises a first conductivity type (paragraph [0048]), and wherein the semiconductor body region (element 13) comprises a second conductivity type (paragraph [0049]); forming a semiconductor source region (element 14) within the semiconductor body region (element 13) (Fig. 3, paragraph [0049]), wherein the semiconductor body region (element 13) separates the semiconductor source region (element 14) from the semiconductor epitaxial layer (element 12) (Fig. 3, paragraph [0049]), and wherein the semiconductor source region (element 14) comprises the first conductivity type (Fig. 3, paragraph [0049]); etching a trench-gate opening (element 30) in an exposed surface of the semiconductor source region (Fig. 7, paragraph [0057]), wherein the trench-gate opening (element 30) comprises a bottom surface (Fig. 7, paragraph [0057]), and wherein the bottom surface comprises the semiconductor epitaxial layer (element 12) (Fig. 7, paragraph [0057]); and implanting a shielding dopant having the second conductivity type by a channeling implant process (Fig. 7, paragraph [0057]), wherein the exposed surface of the semiconductor source region (element 14) is exposed to the shielding dopant during the channeling implant process (Fig. 7), and wherein the shielding dopant forms the trench bottom protective region (element 16) at the bottom surface of the trench-gate opening (element 30) (Fig. 7, paragraph [0057]). Regarding claim 2, Ebiike discloses the method of Claim 1, wherein the channeling implant process accelerates the shielding dopant toward the MOSFET device at a low ion energy (Fig. 7, paragraph [0057]). Regarding claim 4, Ebiike discloses the method of Claim 1, wherein the channeling implant process accelerates the shielding dopant toward the MOSFET device at an implant angle (Fig. 7, paragraph [0057]), and wherein the implant angle is measured relative to a direction normal to a surface of the MOSFET device (Fig. 7, paragraph [0057]). Regarding claim 6, Ebiike discloses the method of Claim 1, further comprising: forming a body contact region (element 15) having the second conductivity type within the semiconductor source region (element 14) (Fig. 3, paragraph [0049]), wherein the body contact region (element 15) is electrically coupled with the semiconductor body region (element 13) (Fig. 3, paragraph [0049]). Regarding claim 7, Ebiike discloses the method of Claim 6, wherein the body contact region (element 15) is doped at a body contact doping concentration (Fig. 3, paragraph [0049]). Regarding claim 8, Ebiike discloses the method of Claim 7, wherein the semiconductor body region (element 13) is doped at a semiconductor body concentration (Fig. 3, paragraph [0048]). Regarding claim 9, Ebiike discloses the method of Claim 8, wherein the body contact (element 15) doping concentration is greater than the semiconductor body (element 13) concentration (Fig. 3, paragraphs [0048-0049]. Regarding claim 10, Ebiike discloses the method of Claim 1, wherein the first conductivity type is an n-type semiconductor (paragraphs [0048-0049]). Regarding claim 11, Ebiike discloses the method of Claim 1, wherein the second conductivity type is a p-type semiconductor (paragraphs [0048-0049]). Regarding claim 12, Ebiike discloses the method of Claim 1, wherein the semiconductor epitaxial layer (element 10) is doped at a first doping concentration (Fig. 2, paragraph [0048]). Regarding claim 13, Ebiike discloses the method of Claim 12, wherein the semiconductor source region (element 14) is doped at a second doping concentration (Fig. 3, paragraph [0049]). Regarding claim 14, Ebiike discloses the method of Claim 13, wherein the first doping concentration is less than the second doping concentration (paragraphs [0048-0049]). Regarding claim 15, Ebiike discloses the method of Claim 1, wherein the semiconductor source region (element 14) is formed using an ion implantation process (Fig. 3, paragraph [0049]). Regarding claim 16, Ebiike discloses the method of Claim 15, wherein a source region lattice structure of the semiconductor source region (element 14) is intentionally damaged during the ion implantation process (Fig. 3, paragraph [0049]), because Applicants do not claim the degree to which damage is being inflicted upon the source region lattice structure, it is assumed that at least one atom will be displaced from the source region lattice structure during the ion implantation process. Regarding claim 17, Ebiike discloses the method of Claim 6, wherein the body contact region (element 15) is formed using an ion implantation process (Fig. 3, paragraph [0049]). Regarding claim 18, Ebiike discloses the method of Claim 17, wherein a body contact region lattice structure of the body contact region (element 15) is intentionally damaged during the ion implantation process (Fig. 3, paragraph [0049]), because Applicants do not claim the degree to which damage is being inflicted upon the body contact region lattice structure, it is assumed that at least one atom will be displaced from the body contact region lattice structure during the ion implantation process . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ebiike et al. (US 20190348524 A1) . Regarding claim 3, the teachings of Ebiike are discussed above. Ebiike does not disclose a low ion energy between 30 kiloelectronvolts and 3000 kiloelectronvolts. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to improve ion implantation process parameters such as ion energy to achieve a desired profile of implanted ions. Regarding claim 4, the teachings of Ebiike are discussed above. Ebiike does not disclose an implant angle between 3.5 degrees and 4.5 degrees. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to improve ion implantation process parameters such as ion implant angle. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /ANGELICA ROSE GALVAN/Examiner, Art Unit 2815 Application/Control Number: 18/411,230 Page 2 Art Unit: 2815 Application/Control Number: 18/411,230 Page 3 Art Unit: 2815 Application/Control Number: 18/411,230 Page 4 Art Unit: 2815
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