Attorney’s Docket Number: T103313US01
Filing Date: 01/12/2024
Claimed Foreign Priority Date: none
Applicants: Lane et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 03/20/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group Invention I (directed to a semiconductor structure), in the reply filed on 03/20/2026, is acknowledged. Applicant cancelled claims 12-22, and indicated that claims 1-11 read on the elected Group Invention. The examiner agrees. Accordingly, pending in this application are claims 1-11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matthews (US5182225).
Regarding Claim 1, Mathews (see, e.g., Figs. 26A-B) shows all aspects of the instant invention, including a semiconductor device comprising:
- a semiconductor substrate (e.g., semiconductor substrate 10) including a bipolar junction transistor (BJT) region (e.g., region including bipolar transistor 20), a complementary field effect transistor (CFET) region (e.g., region including P channel FET 40 and N channel FET 30), and a transition region between the BJT region and the CFET region (e.g., region between 20 and 30, and comprising polysilicon members 36)
- a BJT (e.g., 20) on the semiconductor substrate in the BJT region
- a field effect transistor (FET) (e.g., one of 30 or 40) on the semiconductor substrate in the CFET region
- a composite structure on the semiconductor substrate in the transition region (e.g., structure composed of at least polysilicon members 36, silicon dioxide regions 57, and isolation region 60), the composite structure comprising a first material that is the same as a gate electrode of the FET (see, e.g., Figs. 8A-B: polysilicon members 36 and FET gates 33,34 are all defined from a same polysilicon layer 31).
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kohli (US2009/0101988).
Regarding Claim 1, Kohli (see, e.g., Fig. 2C) shows all aspects of the instant invention, including a semiconductor device comprising:
- a semiconductor substrate (e.g., semiconductor substrate 202) including a bipolar junction transistor (BJT) region (e.g., region including bipolar transistor 224), a complementary field effect transistor (CFET) region (e.g., region including PMOS transistor 210 and NMOS channel transistor 212), and a transition region between the BJT region and the CFET region (e.g., region 218)
- a BJT (e.g., bipolar npn transistor) on the semiconductor substrate in the BJT region
- a field effect transistor (FET) (e.g., one of PMOS or NMOS transistors) on the semiconductor substrate in the CFET region
- a composite structure on the semiconductor substrate in the transition region (e.g., structure composed of at least polysilicon body 220 and sidewall spacer material 222), the composite structure comprising a first material that is the same as a gate electrode of the FET (see, e.g., Figs. 2C: gates of NMOS/PMOS transistors and polysilicon body 220 are of a same polysilicon material).
Allowable Subject Matter
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose BiCMOS semiconductor devices with transition structures between CMOS and BJT regions, and having aspects similar to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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