DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed January 12, 2024.
Claims 1-13 and 21 are pending. Claims 14-20 are withdrawn due to an Election/Restriction Requirement. Claims 1 and 21 are independent.
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on August 4, 2026 is acknowledged. The traversal is on the ground(s) that the elected and non-elected Species are not patentably distinct because the Species are directed to complementary and interrelated aspects of unified subject matter and function together to improve operations in a single device or system. This is not found persuasive because although the Species are directed to a single device or system the device shown in Figure 3 (Species I claims 1-13 and 21) requires down source select transistor of all string groups connected in common through the down source select line, a first up source select transistors group of all strings groups connected in common through a first up source select line, and a second up source select transistor group of all strings groups connected in common through a second up source select line. For Species II (claims 14-17), Figure 9 shows four up source select transistor groups and each group comprising an independent up source select line. For Species III (claims 18-20), Figure 10 shows an even down source select transistor group connected to an even down source select line and an odd down source select transistor group connected to an odd down source select line. Therefore, the species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on February 26, 2024.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 12, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (U.S. 2019/0189216; hereinafter “Baek”).
Regarding independent claim 1, Baek discloses a semiconductor memory device (Fig. 1) comprising:
a first string group (Fig. 3 shows a plurality of cell strings that goes from CS11-CS21 connected to bit line BL1, a first string group can be represented by cell strings CS11-CS16) including a plurality of first memory strings (Fig. 3: CS11-CS16) connected in parallel between a bit line (Fig. 3: BL1) and a source line (Fig. 3: CSL); and
a second string group (Fig. 3 shows a plurality of cell strings that goes from CS11-CS21 connected to bit line BL1, a second string group can be represented by cell strings CS17-CS21) including a plurality of second memory strings (Fig. 3: CS17-CS21) connected in parallel between the bit line (Fig. 3: BL1) and the source line (Fig. 3: CSL);
wherein each of the plurality of first memory strings and the plurality of second memory strings includes at least one down source select transistor (Fig. 3: SST1), at least one first up source select transistor (Fig. 3: SST2), and at least one second up source select transistor (Fig. 3: SST3); and
wherein the at least one first up source select transistor of each of the plurality of first memory strings is programmed to a first state (Fig. 10B: SST2), and the at least one first up source select transistor of each of the plurality of second memory strings is programmed to a second state (Fig. 10B: SST3).
Regarding claim 2, Baek disclose the limitations with respect to claim 1.
As discussed above, Baek’s semiconductor memory device is substantially identical in structure to the claimed “semiconductor memory device,” where the differences reside only in the remaining limitations relating to function of “the at least one second up source select transistor of each of the plurality of first memory strings is programmed to the second state, and the at least one second up source select transistor of each of the plurality of second memory strings is programmed to the first state.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Baek’s semiconductor memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 3, Baek discloses wherein the first state is an erase state and the second state is a program state (see pages 5-6, par. 0090-0091).
Regarding claim 5, Baek discloses wherein each of the plurality of first memory strings and the plurality of second memory strings includes a drain select transistor coupled to the bit line (Fig. 3: DST1-DST3 coupled to BL1); and
the drain select transistors of the plurality of first memory strings and the plurality of second memory strings are electrically coupled to different drain select lines (Fig. 3: DSL1 and DSL2).
Regarding claim 7, Baek discloses wherein the plurality of first memory strings are alternately arranged with the plurality of second memory strings (see Fig. 3).
Regarding independent claim 21, Baek discloses a semiconductor memory device (Fig. 1) comprising:
a first string group (Fig. 3 shows a plurality of cell strings that goes from CS11-CS21 connected to bit line BL1, a first string group can be represented by cell strings CS11-CS16) including at least one first memory string (Fig. 3: CS11-CS16) connected in parallel between a bit line (Fig. 3: BL1) and a source line (Fig. 3: CSL); and
a second string group (Fig. 3 shows a plurality of cell strings that goes from CS11-CS21 connected to bit line BL1, a second string group can be represented by cell strings CS17-CS21) including at least one second memory string (Fig. 3: CS17-CS21) connected in parallel between the bit line (Fig. 3: BL1) and the source line (Fig. 3: CSL);
wherein the at least one first memory string and the at least one second memory string each include at least one down source select transistor (Fig. 3: SST1), at least one first up source select transistor (Fig. 3: SST2), and at least one second up source select transistor (Fig. 3: SST3);
wherein the at least one first up source select transistor of the at least one first memory string is programmed to a first state (Fig. 10B: SST2), and the at least one first up source select transistor of the at least one second memory string is programmed to a second state (Fig. 10B: SST3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (U.S. 2019/0189216; hereinafter “Baek”) in view of Lee (U.S. 2017/0092364).
Regarding claim 4, Baek discloses the limitations with respect to claim 1.
However, Baek is silent with respect to wherein a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the first string group is different from a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the second string group.
Similar to Baek, Lee teaches a semiconductor memory device (Fig. 1) comprising a plurality of string groups (Fig. 4: MB1-MB4) each including a plurality of memory strings (see page , par. 0045), and each memory string comprises a plurality of source select transistors (Fig. 4: GR1 and GR2).
Furthermore, Lee teaches a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the first string group is different from a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the second string group (see page 3, par. 0050-0051).
Since Lee and Baek are from the same field of endeavor, the teachings described by Lee would have been recognized in the pertinent art of Baek.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lee with the teachings of Baek for the purpose of improve the reliability of a memory system, see Lee’s page 7, par. 0090.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, there is no teaching or suggestion in the prior art of record to provide the recited at least one down source select transistor of the plurality of first memory strings and at least one down source select transistor of the plurality of second memory strings share one down source select line, at least one first up source select transistor of the plurality of first memory strings and at least one first up source select transistor of the plurality of second memory strings share one first up source select line, and at least one second up source select transistor of the plurality of first memory strings and at least one second up source select transistor of the plurality of second memory strings share one second up source select line.
Claims 8-13 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 8, there is no teaching or suggestion in the prior art of record to provide the recited steps of programming the at least one second up source select transistor of the plurality of first memory strings to a first state, programming the at least one second up source select transistor of the plurality of second memory strings to a second state, wherein the at least one first up source select transistor of the plurality of first memory strings and the at least one first up source select transistor of the plurality of second memory strings are programmed based on a first up source select line, and wherein the at least one second up source select transistor of the plurality of first memory strings and the at least one second up source select transistor of the plurality of second memory strings are programmed based on a second up source select line, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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