DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-8, 11, 15-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHEN (US 20230307330).
Regarding claim 1, CHEN discloses an electronic device, comprising:
a substrate (the substrate below devices 701-706 comprising 400, 500, see fig 21A, para 71, 72 and 117) comprising:
a first side (the top side of 400, see fig 21A, para 71) comprising a peripheral portion (the portion of the top side of 400 that surround 701 and 702, see fig 21A, para 144) and a central portion (the portion of the top side of 400 overlapping with 701 and 702, see fig 21A) surrounded by the peripheral portion;
a second side (the bottom side of 400, see fig 21A para 71) opposite to the first side;
a dielectric structure (fig 21A, 460, para 161); and
a conductive structure (the via structures 486, see fig 21A, para 65);
a first electronic component comprising a first semiconductor die (the die 701, see fig 21A, para 144) comprising:
a component first side attached to the conductive structure at the first side of the substrate in the central portion (the bottom side of 701 which is attached to 400, see fig 21A);
a component second side opposite to the component first side (the top side of 701, see fig 21A); and
a component lateral side connecting the component first side to the component second side (the side surface of 701, see fig 21A);
a second electronic component attached to the first side of the substrate in the peripheral portion (the die 705, see fig 21A, para 84);
an encapsulant (fig 21A, 760, para 89) covering the second electronic component and the peripheral portion of the first side of the substrate (760 covers the top of 705 and the side surfaces of 701, see fig 21A),
wherein the second side of the first electronic component is exposed from a top side of the encapsulant (the top surface of 701 is exposed from 760, see fig 21A), and
wherein the top side of the encapsulant comprises a substantially planar top side (the top side of 760 is substantially planar, see fig 21A);
a first adhesive (the adhesive 293, see fig 21A, para 124);and
a stiffener (fig 21A, 294, para 124) attached to the top side of the encapsulant in the peripheral portion with the first adhesive,
wherein:
the encapsulant abuts the component lateral side of the first semiconductor die without overlapping or covering the component second side of the first semiconductor die, so that the component second side is exposed from the encapsulant (760 is directly in contact with the side surface of 701 and does not cover the top surface of 701, see fig 21A); and
the component second side of the first semiconductor die is devoid of the stiffener and the first adhesive (the top surface of 701 is not covered by 293 or 294).
Regarding claim 2, CHEN discloses the electronic device of claim 1,wherein:
the stiffener comprises a first width (the left portion of 294 has a first horizontal width, see fig 21A, para 124);
the encapsulant in the peripheral portion comprises a second width (the horizontal width from the left side of 760 to the side surface of 701 in fig 21A);
the second width is greater than the first width (760 has a wider horizontal width than 294, see fig 21A); and
a portion of the substantially planar top side of the encapsulant laterally adjacent to the first semiconductor die is exposed from the stiffener (a portion of the top surface of 760 beside 701 is not covered by 294, see fig 21A).
Regarding claim 7, CHEN discloses the electronic device of claim 1, wherein: the component second side of the first semiconductor die and the substantially planar top side of the encapsulant are substantially coplanar (the top surfaces of 701 and 760 are substantially coplanar, see fig 21A).
Regarding claim 8, CHEN discloses the electronic device of claim 1, further comprising:
a second semiconductor die (702, see fig 21A, para 83) comprising:
a second component first side attached to the conductive structure at the first side of the substrate in the central portion (702 is attached to 400 in the central portion, see fig 21A) and laterally spaced apart from the first semiconductor die such that the first semiconductor die is interposed between the stiffener and the second semiconductor die (702 is spaced apart from 701, and a line can be drawn from 701 to 294 that passes through 702, see fig 21A);
a second component second side opposite to the second component first side (the top side of 702, see fig 21A); and
a second component lateral side connecting the second component first side to the second component second side (the side surface of 702, see fig 21A),
wherein:
the encapsulant is interposed between the component lateral side and the second component lateral side (760 is between 710 and 702, see fig 21A); and
the second component second side is exposed from and is substantially coplanar with the substantially planar top side of the encapsulant (the top side of 702 is exposed from 760, see fig 21A).
Regarding claim 11, CHEN discloses an electronic device, comprising:
a substrate (the substrate below devices 701-706 comprising 400, 500, 260, 280 and 210, see fig 21A, para 71, 72 and 117) comprising:
a first side (the top side of 400, see fig 21A, para 71) comprising a peripheral portion (the portion of the top side of 400 that surround 701 and 702, see fig 21A, para 144) and a central portion (the portion of the top side of 400 overlapping with 701 and 702, see fig 21A) surrounded by the peripheral portion;
a second side (the bottom side of 400, see fig 21A para 71) opposite to the first side;
a dielectric structure (fig 21A, 460, para 161); and
a conductive structure (the via structures 486, see fig 21A, para 65);
a first electronic component comprising a first semiconductor die (the die 701, see fig 21A, para 144) comprising:
a component first side attached to the conductive structure at the first side of the substrate in the central portion (the bottom side of 701 which is attached to 400, see fig 21A);
a component second side opposite to the component first side (the top side of 701, see fig 21A); and
a component lateral side connecting the component first side to the component second side (the side surface of 701, see fig 21A);
a second electronic component attached to the first side of the substrate in the peripheral portion (the die 705, see fig 21A, para 84);
an encapsulant (fig 21A, 760, para 89) covering the second electronic component and the peripheral portion of the first side (760 covers the top of 705 and the side surfaces of 701, see fig 21A),
wherein the second side of the first electronic component is exposed from a top side of the encapsulant (the top surface of 701 is exposed from 760, see fig 21A), and
wherein the top side of the encapsulant comprises a substantially planar top side (the top side of 760 is substantially planar, see fig 21A);
a first adhesive (the adhesive 293, see fig 21A, para 124);and
a stiffener (fig 21A, 294, para 124) attached to the top side of the encapsulant in the peripheral portion with the first adhesive,
wherein: the encapsulant abuts the component lateral side of the first semiconductor die without overlapping or covering the component second side of the first semiconductor die such that the component second side is exposed from; (760 is directly in contact with the side surface of 701 and does not cover the top surface of 701, see fig 21A);
the stiffener comprises a first width (the horizontal width of the left part of 294 in fig 21A);
the encapsulant in the peripheral portion comprises a second width (the horizontal width from the left side of 760 to the side surface of 701 in fig 21A);
the second width is greater than the first width (the horizontal width of 760 in fig 21A is greater than a width of 294, see fig 21A); and
a portion of the substantially planar top side of the encapsulant laterally adjacent to the first semiconductor die is exposed from the stiffener (a portion of the top side of 760 next to 701 is not covered by 294, see fig 21A).
Regarding claim 15, CHEN discloses the electronic device of claim 11,wherein: the component second side of the first semiconductor die and the substantially planar top side of the encapsulant are substantially coplanar (top surfaces of 701 and 760 are substantially coplanar, see fig 21A)..
Regarding claim 16, CHEN discloses the electronic device of claim 11, further comprising:
a second semiconductor die (702, see fig 21A, para 83) comprising:
a second component first side directly attached to the conductive structure at the first side of the substrate in the central portion (702 is attached to 400 in the central portion, see fig 21A) and laterally spaced apart from the first semiconductor die such that the first semiconductor die is interposed between the stiffener and the second semiconductor die (702 is spaced apart from 701, and a line can be drawn from 701 to 294 that passes through 702, see fig 21A);
a second component second side opposite to the second component first side (the top side of 702, see fig 21A); and
a second component lateral side connecting the second component first side to the second component second side (the side surface of 702, see fig 21A),
wherein: the encapsulant is interposed between the component lateral side and the second component lateral side (760 is between 710 and 702, see fig 21A); and
the second component second side is exposed from and is substantially coplanar with the substantially planar top side of the encapsulant (the top side of 702 is exposed from 760, see fig 21A).
Regarding claim 17, CHEN discloses a method of manufacturing an electronic device, comprising:
providing a substrate (the substrate below devices 701-706 comprising 400, 500, 260, 280 and 210, see fig 21A, para 71, 72 and 117) comprising:
a first side (the top side of 400, see fig 21A, para 71) comprising a peripheral portion (the portion of the top side of 400 that surround 701 and 702, see fig 21A, para 144) and a central portion (the portion of the top side of 400 overlapping with 701 and 702, see fig 21A) surrounded by the peripheral portion;
a second side (the bottom side of 400, see fig 21A para 71) opposite to the first side;
a dielectric structure (fig 21A, 460, para 161); and
a conductive structure (the via structures 486, see fig 21A, para 65);
providing a first electronic component (the die 701, see fig 21A, para 144) comprising:
a component first side attached to the conductive structure at the first side of the substrate in the central portion (the bottom side of 701 which is attached to 400, see fig 21A);
a component second side opposite to the component first side (the top side of 701, see fig 21A); and
a component lateral side connecting the component first side to the component second side (the side surface of 701, see fig 21A);
providing a second electronic component coupled to the first side of the substrate in the peripheral portion (the die 705, see fig 21A, para 84);
providing an encapsulant (fig 21A, 760, para 89) covering the second electronic component and the peripheral portion of the first side (760 covers the top of 705 and the side surfaces of 701, see fig 21A),
wherein the second side of the first electronic component is exposed from a top side of the encapsulant (the top surface of 701 is exposed from 760, see fig 21A), and
wherein the top side of the encapsulant comprises a substantially planar top side (the top side of 760 is substantially planar, see fig 21A);
providing a first adhesive (the adhesive 293, see fig 21A, para 124); and
attaching a stiffener (fig 21A, 294, para 124) to the top side of the encapsulant in the peripheral portion with the first adhesive,
wherein:
the encapsulant abuts the component lateral side of the first electronic component without overlapping or covering the component second side such that the component second side is exposed from the encapsulant (760 is directly in contact with the side surface of 701 and does not cover the top surface of 701, see fig 21A);
the stiffener comprises a first width (the horizontal width of the left part of 294 in fig 21A);
the encapsulant in the peripheral portion comprises a second width (the horizontal width from the left side of 760 to the side surface of 701 in fig 21A);
the second width is greater than the first width (the horizontal width of 760 in fig 21A is greater than a width of 294, see fig 21A); and
a portion of the substantially planar top side of the encapsulant laterally adjacent to the first electronic component is exposed from the stiffener (a portion of the top side of 760 next to 701 is not covered by 294, see fig 21A).
Regarding claim 20, CHEN discloses the method of claim 17, wherein:
providing the encapsulant comprises providing the component second side of the first electronic component and the substantially planar top side of the encapsulant substantially coplanar (top surfaces of 701 and 760 are substantially coplanar, see fig 21A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (US 20230307330) in view of LI (US 20150001701).
Regarding claim 3, CHEN discloses the electronic device of claim 2.
CHEN fails to explicitly disclose a device, wherein the stiffener comprises a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width.
LI teaches a device, wherein the stiffener comprises a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width (the inner edge of the stiffener 202 is sloped such that its highest width is at its bottom near adhesive 306 and its top width is smaller, see fig 3, para 45).
CHEN and LI are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN with the layer shape of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN with the layer shape of LI in order to improve carrier flatness (see LI para 23).
Regarding claim 12, CHEN discloses the electronic device of claim 11.
CHEN fails to explicitly disclose a device, wherein:
the stiffener comprises a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width.
LI teaches a device, wherein:
the stiffener comprises a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width (the inner edge of the stiffener 202 is sloped such that its highest width is at its bottom near adhesive 306 and its top width is smaller, see fig 3, para 45).
CHEN and LI are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN with the layer shape of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN with the layer shape of LI in order to improve carrier flatness (see LI para 23).
Regarding claim 18, CHEN discloses the method of claim 17.
CHEN fails to explicitly disclose a device, wherein:
providing the stiffener comprises providing the stiffener comprising a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width.
LI teaches a device, wherein:
providing the stiffener comprises providing the stiffener comprising a sloped inside edge such that the stiffener has the first width proximate to the first adhesive and a third width distal to the first adhesive that is less than both the first width and the second width (the inner edge of the stiffener 202 is sloped such that its highest width is at its bottom near adhesive 306 and its top width is smaller, see fig 3, para 45).
CHEN and LI are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN with the layer shape of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN with the layer shape of LI in order to improve carrier flatness (see LI para 23).
Claim(s) 4, 6, 13, 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (US 20230307330) in view of LI (US 20150001701) and further in view of PARK (US 20220013496).
Regarding claim 4, CHEN and LI disclose the electronic device of claim 2.
CHEN and LI fail to explicitly disclose a device, further comprising:
a second adhesive;
a heat sink attached to the stiffener with the second adhesive; and
a thermal interface material (a TIM) interposed between the second side of the first semiconductor die and the heat sink;
wherein: the TIM covers both the component second side of the first semiconductor die and the portion of the substantially planar top side of the encapsulant exposed from the stiffener.
PARK teaches a device, further comprising:
a second adhesive (165, see fig 6, para 50);
a heat sink attached to the stiffener with the second adhesive (heat sink 166 is at least indirectly attached to 161 by 165, see fig 6, para 50); and
a thermal interface material (a TIM) interposed between the second side of the first semiconductor die and the heat sink (TIM 163 connects 166 to 110, which comprises a die 122 and an encapsulant 130, see fig 6-7, para 29);
wherein: the TIM covers both the component second side of the first semiconductor die and the portion of the substantially planar top side of the encapsulant exposed from the stiffener (163 covers the entire top surface of 110 which is both 122 and 130, see fig 6-7, para 29).
CHEN, LI and PARK are analogous art because they both are directed towards semiconductor interconnect device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN and LI with the heat sink and TIM of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN and LI with the heat sink and TIM of PARK in order to reduce cracks (see PARK para 58).
Regarding claim 6, CHEN and LI disclose the electronic device of claim 4.
CHEN and LI fail to explicitly disclose a device, wherein: the stiffener comprises a ring shape that defines a central recess over the first electronic component; and the TIM is within the central recess.
PARK teaches a device, wherein: the stiffener comprises a ring shape that defines a central recess over the first electronic component; and the TIM is within the central recess (161 is ring shaped and 163 is inside 161, see fig 1 and 6).
CHEN, LI and PARK are analogous art because they both are directed towards semiconductor interconnect device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN and LI with the heat sink and TIM of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN and LI with the heat sink and TIM of PARK in order to reduce cracks (see PARK para 58).
Regarding claim 13, CHEN and LI disclose the electronic device of claim 12.
CHEN and LI fail to explicitly disclose a device, further comprising:
a second adhesive;
a heat sink attached to the stiffener with the second adhesive; and
a thermal interface material (a TIM) interposed between the second side of the first semiconductor die and the heat sink;
wherein:
the second adhesive extends to the third width; and
the TIM covers both the component second side of the first semiconductor die and the portion of the substantially planar top side of the encapsulant exposed from the stiffener.
PARK teaches a device, further comprising:
a second adhesive (162, see fig 6, para 50);
a heat sink attached to the stiffener with the second adhesive (heat sink 166 is at least indirectly attached to 161 by 162, see fig 6, para 50); and
a thermal interface material (a TIM) interposed between the second side of the first semiconductor die and the heat sink (TIM 163 connects 166 to 110, which comprises a die 122 and an encapsulant 130, see fig 6-7, para 29);
wherein:
the second adhesive extends to the third width (the width of 162 is the top width of 161, see fig 6); and
the TIM covers both the component second side of the first semiconductor die and the portion of the substantially planar top side of the encapsulant exposed from the stiffener (163 covers the entire top surface of 110 which is both 122 and 130, see fig 6-7, para 29).
CHEN, LI and PARK are analogous art because they both are directed towards semiconductor interconnect device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN and LI with the heat sink and TIM of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN and LI with the heat sink and TIM of PARK in order to reduce cracks (see PARK para 58).
Regarding claim 14, CHEN and LI disclose the electronic device of claim 13.
CHEN and LI fail to explicitly disclose a device, wherein:
the first adhesive, the stiffener, and the second adhesive define a central recess over the first semiconductor die; and
the TIM is confined to the central recess without overlapping onto a top side of the second adhesive.
PARK teaches a device, wherein:
the first adhesive, the stiffener, and the second adhesive define a central recess over the first semiconductor die (160, 161 and 162 form a ring, see fig 1 and 6); and
the TIM is confined to the central recess without overlapping onto a top side of the second adhesive (163 is inside 161 and does not overlap 162 vertically, see fig 6).
CHEN, LI and PARK are analogous art because they both are directed towards semiconductor interconnect device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN and LI with the heat sink and TIM of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN and LI with the heat sink and TIM of PARK in order to reduce cracks (see PARK para 58).
Regarding claim 19, CHEN and LI disclose the method of claim 18.
CHEN and LI fail to explicitly disclose a device, further comprising:
providing a second adhesive extending to the third width;
providing a thermal interface material (a TIM) over the first electronic component and over the portion of the substantially planar top side of the encapsulant laterally adjacent to the first electronic component that is exposed from the stiffener; and
attaching a heat sink to the stiffener with the second adhesive and over the TIM.
PARK teaches a device, further comprising:
providing a second adhesive extending to the third width (162, see fig 6, para 50);
providing a thermal interface material (a TIM) over the first electronic component and over the portion of the substantially planar top side of the encapsulant laterally adjacent to the first electronic component that is exposed from the stiffener (TIM 163 connects 166 to 110, which comprises a die 122 and an encapsulant 130, see fig 6-7, para 29); and
attaching a heat sink to the stiffener with the second adhesive and over the TIM (heat sink 166 is at least indirectly attached to 161 by 162, see fig 6, para 50).
CHEN, LI and PARK are analogous art because they both are directed towards semiconductor interconnect device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN and LI with the heat sink and TIM of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN and LI with the heat sink and TIM of PARK in order to reduce cracks (see PARK para 58).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (US 20230307330) in view of LI (US 20150001701) and PARK (US 20220013496) and further in view of SHEN (US 20200350231).
Regarding claim 5, CHEN, PARK and LI disclose the electronic device of claim 4.
CHEN, PARK and LI fail to explicitly disclose a device, wherein: the TIM comprises a liquid TIM.
SHEN teaches a device, wherein: the TIM comprises a liquid TIM (151 can be a liquid TIM, see fig 2, para 33).
CHEN, PARK, LI and SHEN are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN, PARK , LI with the liquid TIM of SHEN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN, PARK , LI with the liquid TIM of SHEN in order to reduce volume change (see SHEN para 66).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (US 20230307330) in view of ARAI (US 20220005773).
Regarding claim 9, CHEN discloses the electronic device of claim 8, further comprising:
a metallization layer provided at both the component second side and the second component second side (the metallization layer comprising 788 and 790, see fig 21A, para 84).
CHEN fails to explicitly disclose a device wherein:
the metallization layer comprises a plurality of sequentially provided sub-layers comprising:
a titanium (Ti) layer comprising a thickness of about 0.1 um to about 0.2 um;
a copper (Cu) layer over the titanium (Ti) layer and comprising a thickness of about 0.1 um to about 0.2 um;
a nickel (Ni) layer over the copper (Cu) layer and comprising a thickness of about 0.2 um to about 0.3 um; and
a gold (Au) layer over the nickel (Ni) layer and comprising a thickness of about 0.05 um to about 0.2 um.
ARAI teaches a device wherein:
the metallization layer (metallization layer 948C, see fig 1, para 29) comprises a plurality of sequentially provided sub-layers comprising (948C can be a Ti/Cu/Ni/Au stack, see fig 1, para 29):
a titanium (Ti) layer (the bottom of 948C can be Ti, see fig 1, para 29) comprising a thickness of about 0.1 um to about 0.2 um;
a copper (Cu) layer over the titanium (Ti) layer (the second of 948C can be Cu, see fig 1, para 29) and comprising a thickness of about 0.1 um to about 0.2 um;
a nickel (Ni) layer over the copper (Cu) layer (the third layer of 948C can be Ni, see fig 1, para 29) and comprising a thickness of about 0.2 um to about 0.3 um; and
a gold (Au) layer over the nickel (Ni) layer (the top of 948C can be Au, see fig 1, para 29) and comprising a thickness of about 0.05 um to about 0.2 um.
CHEN and ARAI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN with the metal layers of ARAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN with the metal layers of ARAI in order to reduce warpage (see ARAI para 110).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the layers in the device of ARAI in order to reduce warpage (see ARAI para 110).
Regarding claim 10, CHEN discloses the electronic device of claim 9, wherein: the substrate comprises a coreless substrate (the device can be a coreless device, see fig 21A, para 115).
CHEN fails to explicitly disclose a device, wherein: the nickel (Ni) layer and the gold (Au) layer are electroplated layers.
ARAI teaches a device, wherein: the nickel (Ni) layer and the gold (Au) layer are electroplated layers (the metal layers can be electroplated, see para 29).
CHEN and ARAI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHEN with the metal layers of ARAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHEN with the metal layers of ARAI in order to reduce warpage (see ARAI para 110).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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