Prosecution Insights
Last updated: October 02, 2026
Application No. 18/412,390

DEVICES, SYSTEMS AND METHODS FOR REDUCING WARPAGE DURING FABRICATION OF DUAL SIDE MOLD MODULES

Non-Final OA §102§103§112
Filed
Jan 12, 2024
Priority
Jan 13, 2023 — provisional 63/439,049
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
425 granted / 572 resolved
+6.3% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
41 currently pending
Career history
611
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
21.9%
-18.1% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Species IA (Claims 1-9 and 12-16) in the reply filed on 06/29/2026 is acknowledged. Claims 10-11, 17-19 and 21 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/29/2026. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a substrate of the packaged module, and lateral side surfaces of a second mold structure of the packaged module” of Claim 16. must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 and 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “the initial thickness sufficiently large to prevent warpage of the assembly where a similar assembly having a first mold layer with the final thickness would warp” The term “similar” in claim 1 is a relative term which renders the claim indefinite. The term “similar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The claim does not specify which parameters the comparator assembly must be similar nor how similar parameters must be. Is it identical substrate, material, demetons, CTE, number of devices? Therefore, person of ordinary skill in the art would not be able determine metes and bounds of the claim. Further, the limitation defines structure by reference to the behavior of an unclaimed hypothetical, non-limiting object rather than by physical or dimensional criteria of the claimed assembly itself. While specification in [0079-0081] discloses threshold thickness and provides multiplier ranges, none of the quantitate guidance has been imported into the claim. Therefore, the limitation as drafted will be considered as functional language without the benefit of the disclosed objective ranges. Claims 2-9 and 12-16 are rejected as being dependent on Claim 1 Claim 8 discloses “followed by a thinning operation”. It is not clear is the Applicant is trying to further liming thinning operation introduced in Claim 1 or introduce an additional thinning operation. For the purposes of examination the Examiner will treat “followed by a thinning operation” as part of thinning operation introduced in Claim 1. Claim 9 is rejected as being dependent on Claim 9. Claims 2, 4, 7 recites the limitation "the one or more operations" in 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination the Examiner will treat "the one or more operations" as-- "the one or more process operations" Claims 16 recites the limitation " the first module layer, substrate panel and second mold layer." in 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination the Examiner will treat " the first module layer, substrate panel and second mold layer." As --the first module layer, substrate panel and a second mold layer.-- Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-6 and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US 2024/0282715 A1). Regarding Claim 1, Chad (Fig. 9-10) discloses a method for manufacturing packaged modules, the method comprising: providing or forming a substrate panel (9-1) having first and second sides (top and bottom), and an array of units (areas of 9-1 for 9-111, 9-113); mounting one or more devices (9-111, 9-113) on the first side of the substrate (top of 9-1) panel for each unit (areas of 9-1 for 9-111, 9-113); forming a first mold layer (encapsulant 9-3 is a warpage-resistant layer configured to prevent the warpage of the substrate 9-1) over the first side of the substrate panel (top of 9-1) to provide an assembly, the first mold layer (9-3) having an initial thickness that is greater than a final thickness, the initial thickness sufficiently large to prevent warpage of the assembly where a similar assembly having a first mold layer with the final thickness would warp; (See thickness of in Fig. 10B) performing one or more process operations on the second side (bottom of 3-1 in 4F) of the substrate panel of the assembly [0167]; and performing a thinning operation to reduce the thickness of the first mold layer (9-3) from the initial thickness to the final thickness (final thickness of 9-3 in Fig, 10K (“a grinding process is conducted to cut along the imaginary line “E3” through the encapsulant 9-3 and the encapsulant 9-5”.) [0175] Regarding Claim 2, Chad (Fig. 9-10) discloses the method of claim 1 wherein the one or more operations performed on the second side of the substrate panel includes forming a plurality of conductive features (9-4) and mounting a device (9-131). (Fig. 10C) Regarding Claim 3, Chad (Fig. 9-10) discloses the method of claim 2 wherein the conductive features on the second side of the substrate panel include an array of solder balls (solder balls on 9-4) or an array of conductive posts. Regarding Claim 4, Chad (Fig. 9-10) discloses the method of claim 2 wherein the one or more operations performed on the second side of the substrate panel further includes forming a second mold layer (9-5) over the second side of the substrate panel. Regarding Claim 5, Chad (Fig. 9-10) discloses the method of claim 4 wherein the one or more operations performed on the second side of the substrate panel further includes performing a thinning operation to reduce the thickness of the second mold layer (6-5, 9-51) to a final value. (Fig. 10K) [0147] Regarding Claim 6, Chad (Fig. 9-10) discloses the method of claim 4 wherein the forming of the second mold layer (9-5) results in the second mold layer covering the device ((9-131) and the conductive features (9-4) on the second side of the substrate panel. (Fig. 10J) Regarding Claim 12, Chad (Fig. 9-10) discloses the method of claim 1 wherein the performing of the one or more process operations on the second side of the substrate panel (bottom of 9-1) is achieved after the forming of the first mold layer (9-3) over the first side of the substrate panel. (top of 9-1) (Fig. 10C) Regarding Claim 13, Chad (Fig. 9-10) discloses the method of claim 12 wherein the performing of the thinning operation to reduce the thickness of the first mold layer (9-3) from the initial thickness to the final thickness is achieved after the performing of the one or more process operations on the second side of the substrate (bottom of 9-1) panel. (Fig. 10K) Regarding Claim 14, Chad (Fig. 9-10) discloses the method of claim 13 wherein the thinning operation includes a grinding operation on the first mold layer. (“a grinding process is conducted to cut along the imaginary line “E3” through the encapsulant 9-3 and the encapsulant 9-5”.) [0175] Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2024/0282715 A1) in view of Huang et al. (US 2021/0305173 A1). Regarding Claim 8, Chad (Fig. 9-10) discloses the method of claim 1 wherein Chad does not explicitly disclose the forming of the first mold layer includes a molding operation that results in a mold thickness that is greater than the initial thickness, followed by a thinning operation to reduce the thickness of the first mold layer from the mold thickness value to the initial thickness. Huang (Fig. 9-1) discloses a forming of a first mold layer (180) includes a molding operation that results in a mold thickness that is greater than an initial thickness, followed by a thinning operation to reduce the thickness of the first mold layer from the mold thickness value to the initial thickness.(“ multi-step grinding process is performed to reduce the thickness of the insulating material 180 until top surfaces of the warpage control patterns”) [0041] The Examiner notes that since the thinning is is multi-step process then first thinning step is considered as “a thinning operation to reduce the thickness of the first mold layer from the mold thickness value to the initial thickness” and the following thinning steps are considered “a thinning operation to reduce the thickness of the first mold layer from the initial thickness to the final thickness” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chad in view of Huang to include the forming of the first mold layer includes a molding operation that results in a mold thickness that is greater than the initial thickness, followed by a thinning operation to reduce the thickness of the first mold layer from the mold thickness value to the initial thickness in order to performed to reduce the thickness of the insulating material [0041] Regarding Claim 9, Chad in view of Huang discloses the method of claim 8 wherein the thinning operation includes a grinding operation on the first mold layer. [0041 Huang] [0175 Chad] Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2024/0282715 A1) in view of Lin et al. (US 2012/0187569 A1). Regarding Claim 15, Chad (Fig. 9-10) discloses the method of claim 1. Chad does not explicitly disclose performing a singulating operation to provide a packaged module corresponding to each of the array of units. Lin discloses performing a singulating operation (Fig. 5U) to provide a packaged module (254) corresponding to each of the array of units (124). [0079] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chad in view of Lin to include performing a singulating operation to provide a packaged module corresponding to each of the array of units in order to singulate the finished wafer into the individual semiconductor die [0032, 0079] Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2024/0282715 A1) in view of Lin et al. (US 2012/0187569 A1) and further in view of Lin (US 2016/0276307 A1; hereinafter Lin/307) Regarding Claim 16, Chad in view of Lin discloses the discloses the method of claim 15 further comprising Chad in view of Lindoes not explicitly disclose forming a shielding layer to substantially cover all exposed surfaces of a first mold structure of each packaged module, lateral side surfaces of a substrate of the packaged module, and lateral side surfaces of a second mold structure of the packaged module, the first mold structure, substrate and second mold structure corresponding to the respective unit portion of the first module layer, substrate panel and second mold layer. Lin/307 (Fig. 7) discloses shielding layer (274) to substantially cover all exposed surfaces of a first mold structure of each packaged module, lateral side surfaces of a substrate of the packaged module (190) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chad in view of Lin and Lin/307 to include forming a shielding layer to substantially cover all exposed surfaces of a first mold structure of each packaged module, lateral side surfaces of a substrate of the packaged module, and lateral side surfaces of a second mold structure of the packaged module, the first mold structure, substrate and second mold structure corresponding to the respective unit portion of the first module layer, substrate panel and second mold layer in order to reduce the effects of EMI and RFI. [0090-0092] Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Specifically, none of the prior art teaches or suggests, alone or in combination, “the one or more operations performed on the second side of the substrate panel further includes performing a thinning operation to expose a surface of each of the conductive features.” in the combination required by the claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Jan 12, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
94%
With Interview (+19.2%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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