DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, including claims 1-16, in the reply filed on 6/12/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 3 objected to because of the following informalities: “one surfaces of the first semiconductor chip”, should read “one surface of the first semiconductor chip”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3,6-7,9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (Pg Pub. No. US 20220045010 A1) in view of Lee (Pg Pub. No. KR 20070076010), and further in view of Chen (Pg Pub. No. US 20140102777 A1).
Regarding Claim 1, Shin teaches a semiconductor package(¶0069, fig 10:1003), comprising:
a redistribution line structure (¶0069, fig 10: RD1) including a redistribution line layer(¶0070, fig 10: IL1, IL2, IL3 and IL4);
a first semiconductor chip (¶0069, fig 10: CH1) disposed above the redistribution line structure (fig 10: CH1 is disposed above RD1)and
a sub-semiconductor package (¶0069, fig 10: 602/700) including a second semiconductor chip (¶0049, fig 10: CH2), the sub-semiconductor package being disposed above the second region of the first semiconductor chip (fig 10: 602/700 disposed above right-side portion of CH1);
a via (¶0071, fig 10:MV1) electrically connecting the sub-semiconductor package with the redistribution line structure (MV1 electrically connects 600/700 to RD1); and
a sealant (¶0035, fig 10:MD1) that seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package (MD1 seals the right side of CH1 and bottom right side of 700),
wherein the sub-semiconductor package is disposed within the second region of the first semiconductor chip (600/700 disposed on the right side CH1).
Shin doesn’t teach a semiconductor chip including a first region with a first thickness and a second region with a second thickness that is less than the first thickness, and the via configured as a silicon through via. Lee teaches a semiconductor chip (page 6, ¶2) first region (fig 4: W2) with a first thickness( fig 4: T1) and a second region (fig 4: W3) with a second thickness (fig 4: T2) that is less than the first thickness (T2 is less than T1) and
a through via (fig 4: 222 through electrode) penetrating the second region of the first semiconductor chip, (222 penetrates W3 of 200).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Shin with the semiconductor chip of Lee to decrease the height of chip package and stacking (Lee page 2, ¶5). Shin and Lee both teach semiconductor chip packages with a semiconductor chip and through via’s, but they fail to teach a silicon through via.
Chen teaches a semiconductor package (¶0006, fig 2G) with a first semiconductor chip (¶0018, fig 2G: 20 interposer), and through silicon via (¶0018, fig 2G: 200) penetrating the second region of the first semiconductor chip (200 penetrating 20 on right side).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor chip package of Shin and Lee with the use of through silicon via’s of Chen to create a dense layout and reduce pitch of contacts on the chip (Chen ¶0006).
Regarding claim 2, Shin and Lee in view of Chen teaches the semiconductor package of claim 1, wherein the first semiconductor chip (Shin CH1) and the sub-semiconductor package (Shin 602/700) are exposed to one surface of the sealant (Shin MD1) (MD1 seals the right side of CH1 and bottom right side of 602/700).
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Regarding claim 3, Shin and Lee in view of Chen teach the semiconductor package of claim 2, wherein on the one surface of the sealant (Shin MD1), one surfaces of the first semiconductor chip (Shin CH1), the sub-semiconductor package (Shin fig 10: 602/700), and the sealant are coplanar with one another (Shin fig 10: The top of MD1, top of CH1 and bottom of 602/700 are coplanar.
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Regarding claim 6, Shin and Lee in view of Chen teaches the semiconductor package of claim 1, wherein when a direction (horizontal) perpendicular to a direction (vertical) from the first region (Lee page 4, ¶0013, fig 4: W2) of the first semiconductor chip (Lee page 6, ¶0002) to the second region (Lee page 4, ¶0013, fig 4: W3) of the first semiconductor chip on a plane (e.g., in a plan view) is a width direction, a width of the first region of the first semiconductor chip and a width of the second region of the first semiconductor chip are substantially equal to one another (Lee page 4 ¶0013, fig 4: W2 and W3 are equal).
Regarding claim 7, Shin and Lee in view of Chen teach the semiconductor package of claim 1, wherein at least a portion of the second region (Shin ¶0034, figs 1/10: HS1/700) is surrounded by the first region (Shin ¶0034 figs 1/10: HS2), and the first region and the second region have a plurality of boundary surfaces (Shin fig 1: In the top view of the semiconductor package HS2 surrounds 700 on the left and bottom sides, also HS2 has 6 sides and 700 has 4 sides).
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Regarding claim 9, Shin and Lee in view of Chen teaches the semiconductor package of claim 1, wherein the first semiconductor chip includes a logic chip (Shin ¶0037, fig 10: CH1), and the second semiconductor chip includes a memory chip (Shin ¶0049, fig 10: CH2).
Regarding claim 10, Shin teaches a semiconductor package, comprising:
a redistribution line structure (¶0069, fig 10: RD1) including a redistribution line layer (¶0070, fig 10: IL1, IL2, IL3, IL4);
a first semiconductor chip disposed above the redistribution line structure and including a body and a connecting pad (Shin ¶0037, fig 10: 310) electrically connected to the redistribution line structure (fig 10: CH1 disposed above RD1 including 310 electrically connected to RD1);
a sub-semiconductor package (¶0069, fig 10: 602/700) disposed above the first semiconductor chip and including a substrate (¶0049 fig 10:S2) having a wiring layer (¶0073 fig 10: 602), a second semiconductor chip (¶0049 fig 10: CH2) disposed above the substrate, and a first sealant sealing (¶0035 fig 10: MD1) at least a portion of the second semiconductor chip (600/700 disposed above CH1 and including S2 having 602, CH2 disposed above S2 on the top right of the package, and MD1 seals CH2 on bottom right);
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a via (¶0071, fig 10: MV1) electrically connecting the sub-semiconductor package to the redistribution line structure (MV1 electrically connects 700 to RD1 on the right of CH1) ; and
a second sealant (¶0049 fig 10: MD2) sealing at least a portion of each of the first semiconductor chip and the sub-semiconductor package (MD2 sealing 700 and CH1 secures the sub-package and CH1 from the edge of the semiconductor package),
wherein the first semiconductor chip includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness, ,
the sub-semiconductor package is disposed above the second region of the first semiconductor chip (700 is disposed above the right side of CH1),
Shin does not teach the via comprises a silicon through via penetrating the first semiconductor chip, the first semiconductor chip comprising a first region with a first thickness and a second region with a second thickness less than the first thickness, or the first region of the first semiconductor chip is exposed to one surface of the second sealant.
Lee teaches the first semiconductor chip (Lee page 6 ¶0002, fig 4: 200) includes a first region with a first thickness (Lee page 4 ¶0012 : T1) and a second region with a second thickness (Lee page 4 ¶0012 : T2) that is less than the first thickness (Lee page 2 ¶0010, fig 4: T2 is less than T1)
the first region of the first semiconductor chip (Lee page 6 ¶0002, fig 4: 200) is exposed to one surface of the second sealant (Lee page 8 ¶5, fig 4: 300 connective member/insulating resin) (Lee page 8 ¶5, fig 4: 200 is exposed to 300)
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Shin with the step like semiconductor chip, and sealant exposure of Lee. It would have been obvious to implement through structure in the right side of the semiconductor chip to achieve a shortened connection between semiconductor chip and package substrates, and to achieve a higher speed transmission signal due to the shortened distance.
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Shin with the semiconductor chip of Lee to decrease the height of chip package and stacking.
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor chip package of Shin with the insulating resin sealant of Lee to provide insulation from conductive package elements, and to encapsulate the two semiconductor chips.
Shin and Lee teach a semiconductor chip package with through via’s, but they both fail to teach and the silicon through via penetrates the second region of the first semiconductor chip. Chen teaches a semiconductor package (¶0006, fig 2G) with a first semiconductor chip (¶0018, fig 2G: 20 interposer), and through silicon via (¶0018, fig 2G: 200) penetrating the second region of the first semiconductor chip (200 penetrating 20 on right side).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor chip package of Shin and Lee with the use of through silicon via’s of Chen to create a dense layout and reduce pitch of contacts on the chip (Chen ¶0006).
Regarding claim 11, Shin in view of Lee and Chen teaches the semiconductor package of claim 10,
wherein the sub-semiconductor package and a first semiconductor chip (Shin fig
10: 602/700)
Shin does not teach the first sub-semiconductor chip is exposed to the one
surface of the second sealant to which the first semiconductor chip is exposed.
Lee teaches a second sealant (Lee fig 4: 300) to which the first semiconductor chip(Lee page 6, ¶0002 is exposed) .
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the sub semiconductor chip package of Shin with the second sealant exposed to both the sub-semiconductor package and the first semiconductor chip to increase stability and increase insulation.
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Regarding claim 12, Shin in view of Lee and Chen teaches the semiconductor package of claim 10, Shin in view of Lee fails to teach a first via pad and a second via pad that are respectively disposed on both surfaces of the body of the first semiconductor chip and are electrically connected to each other by the silicon through via.
Chen teaches a first via pad (Chen ¶0018, fig 2G: 210 outermost layer of 21) and a second via pad (Chen ¶0026, fig 2G: 240) that are respectively disposed on both surfaces of the body of the first semiconductor chip (Chen ¶0018, fig 2G: 20) and are electrically connected to each other by the silicon through via (Chen ¶0018, fig 2G: 200) (Chen ¶0026, fig 2G: 210 and 240 are opposite 20 and are electrically connected by 200).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor chip package of Shin, and chip step of Lee with the via pads and through silicon via construction of Chen to decrease package size and reduce resistance by minimizing the distance of the direct connections.
Regarding claim 13, Shin in view of Lee and Chen teaches the semiconductor package of claim 12, further comprising a bump (Shin, ¶0050 fig 10:320) disposed above the first semiconductor chip (Shin, fig 10: CH1) and electrically connecting the first via pad (Shin, fig 10: 350) to the substrate (Shin, fig 10:S2) (Shin ¶0050 fig 10: 320 disposed above CH1 and electrically connecting 350 to S2).
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Regarding claim 14, Shin and Lee in view of Chen teaches the semiconductor package of claim 12, further comprising a bump (Shin ¶0050, fig 10: 320) disposed on the redistribution line structure (Shin ¶0069, fig 10: RD1) and electrically connecting at least one of the connecting pad (Shin ¶0070, fig 10: SL) and the second via pad (Shin ¶0074, fig 10: 350) to the redistribution line structure (Shin RD1) (320 located above RD1 and connecting 350 to 348).
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Regarding claim 15, Shin and Lee in view of Chen teach the semiconductor package of claim 12, wherein the first via pad (Shin ¶0074, fig 10: 350) directly contacts at least one wiring pattern (Shin ¶0073, fig 10: 602 wiring layer) included in the wiring layer of the substrate (S2) (350 directly contacts wiring patterns of 602 and 602 is included in 602/700 substrate).
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Regarding claim 16, Shin in view of Lee and Chen teach the semiconductor package of claim 12, wherein at least one of the connecting pad (Shin ¶0070, fig 10: SL) and the second via pad (Shin ¶0074, fig 10: 348) directly contacts at least one redistribution line pattern (Shin¶0070, fig 10: 344/346) included in the redistribution line layer (Shin ¶0070, fig 10: IL1, IL2, IL3 and IL4). (Shin fig 10: SL and 348 directly contact 344 located in IL1-IL4).
Claim(s) 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Lee and Chen above, and further in view of Thacker (Pg Pub No. US 20160216445 A1).
Regarding claim 4, Shin and Lee in view of Chen teach the semiconductor package of claim 1,
Shin Lee and Chen teaches a semiconductor chip with thickness (Lee T1) and
thickness (Lee T2).
Shin, Lee and Chen do not explicitly teach wherein the thickness of the second region of the first semiconductor chip is within a range of from 50 μm to 400 μm.
Thacker teaches a semiconductor package with an interposer chip (¶0037, fig 1
118-1)
wherein the thickness of the first region of the first semiconductor chip is within a range from 50 μm to 400 μm (¶0037 fig 1: thickness of 118-1 is between 100 μm and 1000 μm).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to optimize the thickness and step formation of the semiconductor chip of Shin in view of Lee and Chen, as a means to shorten the distance of interconnections thereby enabling high-density, and high-performance systems (Thacker ¶0005).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, determining the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the instant case, modifying the semiconductor chip of Shin in view of Lee and Chen to arrive at the claimed thickness of “50 μm to 400 μm” would be a matter of routine optimization.
Regarding claim 5, Shin, Lee and Chen teach the semiconductor package of claim
1,
Shin Lee and Chen teaches a semiconductor chip with thickness (Lee T1) and
thickness (Lee T2).
Shin Lee and Chen do not explicitly teach wherein the thickness (Lee T1) of the
first region of the first semiconductor chip is within a range from 500 μm to 800 μm.
Thacker teaches a semiconductor package with an interposer chip (¶0037, fig
118-1)
wherein the thickness of the first region of the first semiconductor chip is within a range from 500 μm to 800 μm (¶0037 thickness of 118-1 is between 100 μm and 1000 μm).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to optimize the thickness of the semiconductor chip of Shen in view of Lee and Chen, as a means to reduce thermo-mechanical stress (Thacker ¶0037).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, determining the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). *** In the instant case, modifying the semiconductor chip of Shin in view of Lee and Chen to arrive at the claimed thickness of “100 μm to 1mm” would be a matter of routine optimization.
The specification contains no disclosure of either the critical nature of the claimed [values/ranges] nor any unexpected results arising therefrom. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960).
Claim(s) 8 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Lee and Chen above, and further in view of Kim et. al. (Pg Pub. No US 20180261576 A1).
Regarding claim 8, Shin in view of Lee and Chen teaches the semiconductor package of claim 1,
Shin Lee and Chen teach a first semiconductor chip with a predetermined
Length (Shin CH1).
Shin Lee and Chen fail to explicitly teach wherein a length of the first semiconductor chip is within a range of from 11 mm to 20 mm.
Kim teaches a first semiconductor chip (¶0104, fig 1: 200) wherein a length is 13mm (¶0056)
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to optimize the length of the semiconductor chip provide a mechanically stable base for the package to be built on.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, determining the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the instant case, adjusting the chip length of Shin in view of Lee and Chen to meet the claimed range of 11 mm to 20 mm involves only routine skill.
The specification contains no disclosure of either the critical nature of the claimed [values/ranges] nor any unexpected results arising therefrom. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
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/LYTESHIA M PRICE/ Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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