Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The Amendment filed 7/1/26 has been entered. Claims 1-20 remain pending in the application. Application’s amendments to the Drawings, Specification, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed 4/1/26.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot and new citations have been provided to teach the amended limitations
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent 10586723 to Kawai et al. (Kawai).
Regarding claim 1, Kawai teaches wherein the wafer storage device comprises a chamber floor, a chamber ceiling, and one or more chamber walls between the chamber floor and the chamber ceiling to define the wafer storage chamber (71 and 72, Figure 10 has these features) wherein the purge system is arranged relative to the wafer storage device such that after the purge gas is conducted into the wafer storage chamber (71 and 72, Figure 10) of the wafer storage device (through tubes 44c and 87, Figure 10): a first portion of the purge gas exits the wafer storage chamber of the wafer storage device through an outlet of the wafer storage device (through 44d, Figure 10); and a second portion of the purge gas exits the wafer storage chamber of the wafer storage device through one or more discontinuities of the wafer storage device to a space external to the wafer storage device (space Sg in Figure 12, also shown unlabeled or labeled differently in Figures 24, and/or 25); and an exhaust device arranged relative the wafer storage device to conduct a measure of the second portion of the purge gas away from the space (88 and 46 and associated walls or the space enclosing Sg, Figures 5 and 10-12), wherein: the exhaust device comprises a floor, a ceiling, and one or more walls between the floor and the ceiling to define an exhaust chamber into which the measure of the second portion of the purge gas is conducted; and the one or more walls of the exhaust device are spaced apart from the one or more chamber walls of the wafer storage device (shown in Figures 5 and 12 and Col. 17 lines 2-4 for 46 and per Figures 11-12, 24, and 25 all show a sealed space which appears to have the walls claimed and at least one is spaced apart from the chamber).
Regarding claims 2 and 10, Kawai teaches the camber floor of the wafer storage device is at a first elevation; the floor of the exhaust device is at a second elevation; and the second elevation is not lower than the first elevation (this is provided dependent on the orientation of the device such as when the device is upside down).
Regarding claim 3, Kawai teaches wherein the one or more walls comprise: a gas entry wall defining one or more first openings (wall with 44d passing through it, Figure 10 or wall with 75, Figure 11); and a gas exit wall defining one or more second openings (wall with openings leading to 87 and 88, Figure 10 or wall with openings leading to 88 and 87, Figure 11).
Regarding claim 4, Kawai teaches the gas entry wall faces and is spaced apart from a first chamber wall of the one or more chamber walls is configured such that the measure of the second portion of the purge gas flows through the one or more first openings into the exhaust chamber; and the gas exit wall is configured such that the measure of the second portion of the purge gas flows out of the exhaust chamber through the one or more second openings (the walls are configured in this manner to allow the function claimed and the gas entry wall is spaced apart from at least one chamber wall of which any can be considered the first chamber wall).
Regarding claim 5, Kawai teaches wherein: the ceiling defines one or more openings (through 44d, Figure 10 and through 94 and 96, Figure 11); and the ceiling is configured such that the measure of the second portion of the purge gas flows through the one or more openings into the exhaust chamber (the ceiling is configured in this manner to allow the function claimed).
Regarding claims 6 and 14, Kawai teaches wherein the exhaust device comprises: a gas conduit configured to conduct the measure of the second portion of the purge gas out of the exhaust chamber (88a or 88, Figure 10).
Regarding claims 7 and 15, Kawai teaches wherein: a semiconductor manufacturing environment is comprised within the space external to the wafer storage device (shown in Figure 2); and the gas conduit is configured to conduct the measure of the second portion of the purge gas to at least one of: a location external to the semiconductor manufacturing environment; or a gas storage device (shown in Figure 10 where 89 and the box containing 46 are external to both).
Regarding claims 8, 16, and 20, Kawai teaches wherein: a plane parallel to at least one of the camber floor of the wafer storage device or the floor of the exhaust device passes through the one or more walls of the exhaust device and the one or more chamber walls of the wafer storage device (a plane parallel to either can be selected to meet this limitation because all orientations are believed to be allowed under this limitation).
Regarding claim 9, Kawai teaches a wafer storage device comprising an inlet through which a gas flows into a wafer storage chamber of the wafer storage device (interior of 71 and 72, Figure 10), the exhaust device spaced apart from the wafer storage device (at least part of the exhaust device is spaced apart which is believed to meet the claim language as this appears to be the orientation provided in the instant application) the rest of claim 9 is taught in claim 1 above.
Regarding claim 11, Kawai teaches the one or more walls comprise: a gas entry wall defining one or more first openings (wall with 75, Figure 11); and a gas exit wall defining one or more second openings (wall with 87 and 88, Figure 11); and the ceiling defines one or more third openings (wall with openings at 94 and 96, Figure 11).
Regarding claim 12, Kawai teaches wherein: a bottommost surface of the wafer storage device is at a first elevation; the floor of the exhaust device is at a second elevation; and the second elevation is not lower than the first elevation (this is provided dependent on the orientation of the device such as when the device is upside down).
Regarding claim 13, Kawai teaches wherein: a plane passes through the one or more walls and walls of the wafer storage device (a plane can be selected to meet this limitation).
Regarding claim 17, Kawai teaches a load port (through 72, Figure 10) and an exhaust device laterally offset from the wafer storage device (dependent on the orientation this is met), the rest of claim 17 is taught be claims 1 and 9 above).
Regarding claim 18, Kawai teaches wherein: the purge system is configured to conduct the purge gas into the wafer storage chamber of the wafer storage device before the semiconductor fabrication process is performed on the one or more semiconductor wafers (gas can be injected through 44c, Applicant has not claimed a controller or any equivalent and therefore the device only needs to be able to perform the function or perform the function. This prior art does both).
Regarding claim 19, Kawai teaches wherein: the purge system is configured to conduct the purge gas into the wafer storage chamber of the wafer storage device after the semiconductor fabrication process is performed on the one or more semiconductor wafers (gas can be injected through 44c, Applicant has not claimed a controller or any equivalent and therefore the device only needs to be able to perform the function or perform the function. This prior art does both).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN S ANDERSON II whose telephone number is (571)272-2055. The examiner can normally be reached M-F 8-5.
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/STEVEN S ANDERSON II/ Primary Examiner, Art Unit 3762
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