Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's amendment/arguments filed on 7/29/26 as being acknowledged and entered. By this amendment claims 1-20 are pending and claims 9 and 16-18 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-8, 10, and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2022/0302109).
Claim 1: Kim teaches (Fig. 2, 34) a semiconductor device, comprising: a first active pattern (F3); a second active pattern (F5) spaced apart at a first distance from the first active pattern; a third active pattern (F2) spaced apart at a second distance from the second active pattern; a first device isolation layer (30) between the first active pattern and the second active pattern; a second device isolation layer (105) between the second active pattern and the third active pattern (F2); a first channel structure (NW) overlapping the first active pattern; a second channel structure (NW) overlapping the second active pattern; a third channel structure (NW) overlapping the third active pattern; and a separation dielectric layer (124) between the first channel structure and the second channel structure, wherein the second active pattern is between the first active pattern and the third active pattern, wherein the first distance is less than the second distance, wherein the separation dielectric layer overlaps the first device isolation layer, and wherein a level of a top surface of the first device isolation layer (30) is higher than a level of a top surface of the second device isolation layer (105), and wherein a level of a bottom surface of the separation dielectric layer (124) is lower than the level of the top surface of the first device isolation layer (105a), and an entire bottom surface of the separation dielectric layer is lower than an entire top surface of the first device isolation layer.
Claim 2: Kim teaches (Fig. 2) a first gate electrode overlapping the first channel structure, wherein a level of a bottom surface of the first gate electrode (G2) is lower than the level of the top surface of the first device isolation layer (105a) and higher than the level of the bottom surface of the separation dielectric layer (124).
Claim 3: Kim teaches (Fig. 2) a level of a bottom surface of the separation dielectric layer is higher than a level of a bottom surface of the first device isolation layer.
Claim 4: Kim teaches the separation dielectric layer [0053] and the first device isolation layer [0098] include different dielectric materials from each other.
Claim 7: Kim teaches (Fig. 2) a width of the first device isolation layer is greater than a width of the separation dielectric layer.
Claim 8: Kim teaches (Fig. 2) a gate electrode overlapping the first channel structure, wherein the first channel structure includes a plurality of semiconductor patterns overlapping each other, wherein a first part of the gate electrode is between the plurality of semiconductor patterns, and wherein a second part of the gate electrode is between the plurality of semiconductor patterns and the separation dielectric layer.
Claim 10: Kim teaches semiconductor device (Fig. 2), comprising: a first active pattern (F3) and a second active pattern (F5) adjacent to each other; a device isolation layer (105) between the first active pattern and the second active pattern; a first channel structure (NW) overlapping the first active pattern; a second channel structure (208) overlapping the second active pattern; a first gate electrode (G2) overlapping the first channel structure; a second gate electrode (G1) overlapping the second channel structure; and a separation dielectric layer (124) between the first channel structure and the second channel structure and between the first gate electrode and the second gate electrode, wherein a level of a bottom surface of the separation dielectric layer is lower than a level of a top surface of the device isolation layer, and an entire bottom surface of the separation dielectric layer is lower than an entire top surface of the device isolation layer.
Claim 12: Kim teaches (Fig. 2) the first channel structure includes a plurality of semiconductor patterns overlapping each other, a first part of the first gate electrode is between the plurality of semiconductor patterns, and a second part of the first gate electrode is between the plurality of semiconductor patterns and the separation dielectric layer.
Claim 13: Kim teaches (Fig. 2) the second part of the first gate electrode overlaps the device isolation layer.
Claim 14: Kim teaches (Fig. 2) the device isolation layer (105) includes a first part and a plurality of second parts protruding from the first part, and a width of the first part of the device isolation layer is greater than a width of each of the plurality of second parts of the device isolation layer.
Claim 15: Kim teaches (Fig. 2) the plurality of second parts of the device isolation layer are spaced apart from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 2022/0302109) and, as applied to claim 5 above, and further in view of More (US PGPub 2023/0253258).
Regarding claim 5, as described above, Kim substantially reads on the invention as claimed, except Kim does not teach a first gate electrode overlapping the first channel structure; and a first upper source/drain pattern connected to the first channel structure, wherein the top surface of the first device isolation layer includes a first top surface and a second top surface the first top surface of the first device isolation layer overlaps the first gate electrode, the second top surface of the first device isolation layer overlaps the first upper source/drain pattern, a level of the first top surface of the first device isolation layer is higher than a level of the second top surface of the first device isolation layer. More teaches a first gate electrode (212) overlapping the first channel structure (208); and a first upper source/drain pattern (210) connected to the first channel structure, wherein the top surface of the first device isolation layer includes a first top surface and a second top surface the first top surface of the first device isolation layer overlaps the first gate electrode, the second top surface of the first device isolation layer overlaps the first upper source/drain pattern, a level of the first top surface of the first device isolation layer is higher than a level of the second top surface of the first device isolation layer (Fig. 1 E, 4D, 5D) to reduce leakage [0012]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by More to have included the claimed limitations to reduce leakage [0012] as taught by More.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 2022/0302109) and More (US PGPub 2023/0253258), as applied to claim 5 above, and further in view of More (CN 116469 912A/US PGPub 2023/0299138).
Regarding claim 6, as described above, More (258) substantially reads on the invention as claimed, except More (258) does not teach gate dielectric layer between the first top surface of the first device isolation layer and the first gate electrode; and a lower cover dielectric layer between the second top surface of the first device isolation layer and the first upper source/drain pattern, wherein the first top surface of the first device isolation layer is in contact with the gate dielectric layer, and wherein the second top surface of the first device isolation layer is in contact with the lower cover dielectric layer. More (138) (Fig. 7, 8D) teaches gate dielectric layer (804) between the first top surface of the first device isolation layer (edge portion of 206 under 212) and the first gate electrode (212); and a lower cover dielectric layer (524) between the second top surface of the first device isolation layer and the first upper source/drain pattern (210), wherein the first top surface of the first device isolation layer is in contact with the gate dielectric layer, and wherein the second top surface of the first device isolation layer is in contact with the lower cover dielectric layer to help control unwanted dopant movement [0012]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by More (258) to have included the claimed limitations to help control unwanted dopant movement [0012] as taught by More (258).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 2022/0302109) and, as applied to claim 10 above, and further in view of Hwang et al. (US PGPub 2024/0347609)
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 11, as described above, Kim substantially reads on the invention as claimed, and Kim teaches (Fig. 2) the level of the bottom surface of the separation dielectric layer is higher than a level of a bottom surface of the device isolation layer. Kim does not teach a level of a bottom surface of the first gate electrode is lower than the level of the top surface of the device isolation layer. Hwang teaches a level of a bottom surface of the first gate electrode (GE1_T) is lower than the level of the top surface of the device isolation layer (11) to improve device performance [0003]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Hwang to have included the claimed limitations to improve device performance [0003] as taught by Hwang.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach all of the limitations of claims 19-20. Claim 20 is dependent on claim 19. Claim 19 is allowable due to the underlined limitation below.
Claim 19: Kim teaches (Fig. 2) semiconductor device, comprising: a first active pattern and a second active pattern adjacent to each other; a device isolation layer between the first active pattern and the second active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a first gate electrode overlapping the first channel structure; a second gate electrode overlapping the second channel structure; a first gate dielectric layer between the first gate electrode and the first channel structure; a second gate dielectric layer between the second gate electrode and the second channel structure; a first upper source/drain pattern connected to the first channel structure; a second upper source/drain pattern connected to the second channel structure; a first lower dielectric pattern between the first channel structure and the first active pattern; a second lower dielectric pattern between the second channel structure and the second active pattern; and a separation dielectric layer between the first channel structure and the second channel structure, between the first gate electrode and the second gate electrode, between the first upper source/drain pattern and the second upper source/drain pattern, and between the first lower dielectric pattern and the second lower dielectric pattern, wherein the separation dielectric layer overlaps the device isolation layer, and wherein the separation dielectric layer and the device isolation layer include different dielectric materials from each other [00563, 0098], and a portion of the first gate dielectric layer extends over and contacts the first lower dielectric pattern, a portion of the second gate dielectric layer extend over and contacts the second lower dielectric pattern, and an uppermost surface of the device isolation layer (105) is coplanar with an uppermost surface of the first lower dielectric pattern and an uppermost surface of the second lower dielectric pattern.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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