Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: Claims 1-8 and 15-20 in the reply filed on 6/29/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 15-16, 20 is/are rejected under 35 U.S.C. 102(a)1 as being anticipated by Lin et al. (US 7759212 B2).
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CLAIM 1. Lin teaches an electronic device comprising:
a substrate 46 having a metal trace layer 44/34 disposed therein;
a die 52/58/64 having an active surface, the die being disposed on a side of the substrate 46 where the active surface of the die is in electrical contact with an exposed surface of the metal trace layer 44/34;
a protective layer 32 disposed on an opposite side of the substrate 46 as the die 52/58/64, the protective layer being disposed on non-metal portions 40 of the substrate; and
a mold compound 68 encapsulating the die 52/58/64 and covering all but one surface of the substrate, where the one surface not covered faces away from the die (Fig. 2d – eg surface which protective layer 32 is disposed.).
CLAIM 2. Lin teaches the electronic device of claim 1, wherein the protective layer overlaps a portion of the exposed surface of the metal trace layer 44/34 disposed in the substrate adjacent to the non-metal portions 40 of the substrate 46and wherein other portions of the exposed surface of the metal trace layer remain exposed for electrical contact 74/72 with an external electronic device 76 (Fig. 2d).
CLAIM 3. Lin teaches the electronic device of claim 2, wherein the substrate comprises a plurality of substrate layers and wherein each of the plurality of substrate layers includes a dielectric layer 40/46 (Fig. 2d).
CLAIM 4. Lin teaches the electronic device of claim 3, wherein the metal trace layer 44/34 is a first metal trace layer, the first metal trace layer being disposed in the dielectric layer of one of the plurality of substrate layers 40/46 (Fig. 2d).
CLAIM 5. Lin teaches the electronic device of claim 4 further comprising a second metal trace layer 44/34 disposed in the dielectric layer of another one of the plurality of substrate layers 40/46 (Fig. 2d).
CLAIM 6. Lin teaches the electronic device of claim 5, wherein the die is disposed on the one of the plurality of substrate layers and electrically communicates with contacts of the first metal trace layer (Fig. 2d).
CLAIM 7. Lin teaches the electronic device of claim 6, wherein the protective layer 32is disposed on an exposed surface of the another one of the plurality of substrate layers 40/46 (Fig. 2d).
CLAIM 8. Lin teaches the electronic device of claim 1, wherein a tensile strength of the protective layer is greater than a tensile strength of the substrate (Lin teaches protective layer 32 may be “layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxy-nitride (SiON), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO)”, and substrate “40 can include any suitable insulation material such as polyimide, benzocyclobutene (BCB), PBO (polybenzoxazoles), epoxy based insulating polymer”. As such, Lin teaches several combinations from the finite amount of combinations of the listed materials that will inherently meat the conditions due to the known properties of the materials. Specifically, Silicon Nitride as the protective layer paired with Polyimide as the substrate; Silicon Dioxide as the protective layer paired with Benzocyclobutene (BCB) as the substrate; or Silicon Oxy-Nitride as the protective layer paired with PBO as the substrate.)
CLAIM 15. Lin teaches an electronic device comprising:
a plurality of substrate layers 40/46;
a die 52/58/64 having an active surface, the die being disposed on a side of the plurality of substrate layers 40/46 where the active surface of the die 52/58/64 is in electrical contact with an exposed metal surface 34/44of the plurality of substrate layers;
a protective layer 32 disposed on an opposite side of the plurality of substrate layers as the die 52/58/64, the protective layer 32 being disposed on non-metal portions 40 of the plurality of substrate layers 40/46; and
a mold compound 68 encapsulating the die 52/58/64 and covering all but one surface of the plurality of substrate layers 40/46, where the one surface not covered faces away from the die (Fig. 2d).
CLAIM 16. Lin teaches the electronic device of claim 15, wherein the protective layer 32 overlaps a portion of the exposed metal surface 34 adjacent to the non-metal portions 40 of the plurality of substrate layers 40/46 and wherein other portions of the exposed metal surface of the plurality of substrate layers remain exposed for electrical contact 72/74 with an external electronic device 76 (Fig. 2d).
CLAIM 20. Lin teaches the electronic device of claim 15, wherein a tensile strength of the protective layer is greater than a tensile strength of the plurality of substrate layers (Lin teaches protective layer 32 may be “layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxy-nitride (SiON), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO)”, and substrate “40 can include any suitable insulation material such as polyimide, benzocyclobutene (BCB), PBO (polybenzoxazoles), epoxy based insulating polymer”. As such, Lin teaches several combinations from the finite amount of combinations of the listed materials that will inherently meat the conditions due to the known properties of the materials. Specifically, Silicon Nitride as the protective layer paired with Polyimide as the substrate; Silicon Dioxide as the protective layer paired with Benzocyclobutene (BCB) as the substrate; or Silicon Oxy-Nitride as the protective layer paired with PBO as the substrate.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over in et al. (US 7759212 B2).
CLAIM 17. Lin teaches the electronic device of claim 15, wherein the plurality of substrate layers includes a first substrate layer comprising a first dielectric layer, a second substrate layer comprising a second dielectric layer, however is silent upon and a third substrate layer comprising a third dielectric layer. However, it would have been obvious to a [PHOSITA] at the time of the invention to provide additional dielectric and metal trace layers. As recognized in Lin, the substrate layers are build-up layers intended to provide complexity, density, and routing. According to the foundational principles of obvious engineering choice, increasing or varying the number of layers in a stacked substrate structure to accommodate varying routing and complexity requirements is considered a predictable variation.
Under the principles of MPEP 2144.04, modifying a device package to simply duplicate or add interchangeable part layers (such as dielectric and trace layers) represents a simple design choice within the skill of the ordinary artisan. Because the additional dielectric layers serve their expected function of providing further insulation and routing capability, the modification yields predictable results. Therefore, adding a third substrate layer to achieve the desired level of complexity would have been obvious.
CLAIM 18. Lin teaches the electronic device of claim 17 further comprising a first metal trace layer disposed in the first dielectric layer, a second metal trace layer disposed in the second dielectric layer, and a third metal trace layer disposed in the third dielectric layer (Fig. 2d – Understood structure of increasing the number of build-up layers. See regarding claim 17.).
CLAIM 19. Lin teaches the electronic device of claim 18, wherein vias from the second metal trace layer electrically connect contacts from the first metal trace layer to terminals of the third metal trace layer, the contacts being electrically connected to the die and the terminals configured to electrically connect to an external electronic device (Fig. 2d).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/9/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898