DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status
The previous specification objection is withdrawn.
The instant Office Action is in response to applicants’ remarks filed on 07/10/2026. Claims 1, 3, 5, 11, 15, 16, 18, and 20 are amended and no new claims have been appended. Claims 1-20 are pending.
Response to Arguments
Applicant’ arguments filed 07/10/2026 are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US Patent No 11,380,651) in view of Park (US Patent No 11,315,905).
Regarding claim 1, Park (US Patent No 11,380,651) teaches A semiconductor package (Figure 1) comprising: a first substrate (base substrate 100, Figure 1, col 3, lines 7-13, teaches The base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks...and the external connection terminals. For example, the base substrate may include a printed circuit board (PCB), a redistribution layer, or the like) comprising a plurality of wires stacked in a plurality of layers in a vertical direction, respectively; a plurality of chip stack structures (chip stack 110 + 120 & chip stack 130 + 140, Figure 1, Col 2, lines 60-61) spaced apart from each other on the first substrate and arranged in a first direction wherein each of the plurality of chip stack structures comprises a plurality of semiconductor chips (first semiconductor chips 110-1 – 110-4, Figure 1, Col 3, lines 48-50 & Col 4, lines 39-40; third semiconductor chips 130-1 – 130-4, Figure 1, Col 7, lines 19-20 & Cols 7 lines 66 – Col 8 line 1) offset-stacked in the first direction and a plurality of wires (first interconnectors 115, Figure 1, Col 4, lines 62-64; third interconnectors 135, Figure 1, Col 8, lines 18-19) connecting the plurality of semiconductor chips to one another, and wherein the plurality of wires stacked in the plurality of layers includes a wiring electrically connecting the processor chip to another chip stack structure of the plurality of chip stack structures, the another chip stack structure being different from the chip stack structure disposed closest to the processor chip (Figure 1, Col 3 lines 7-20 + Col 4 lines 18-32, teaches The base substrate 100 may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks 110, 120, 130 and 140 and the printed circuit board 150, and the external connection terminals 180. For example, the base substrate 100 may include a printed circuit board (PCB), a redistribution layer, or the like...The third interconnectors 135 may electrically connect the third semiconductor chips 130-1 to 130-4 with one another and electrically connect the third chip stack 130 with the base substrate 100. In the present embodiment, the third interconnectors 135 may be bonding wires which connect the third chip pads 134 adjacent in the vertical direction with one another and connect the third chip pads 134 of the lowermost third semiconductor chip 130-1 to the third conductive pads 103-3. In other words, the third chip stack 130 may be electrically connected to the base substrate 100 by wire bonding. However, it is to be noted that the present embodiment is not limited thereto, and various types of electrical interconnectors such as leads, conductive tapes, conductive spacers and through electrodes may be used as the third interconnectors 135...The base substrate 100 may include conductive pads 103-1, 103-2, 103-3 and 103-4 disposed on the first surface 101, and conductive pads 104 disposed on the second surface 102. The conductive pads 103-1, 103-2, 103-3 and 103-4 may be for electrically connecting the first to fourth chip stacks 110, 120, 130 and 140 and the printed circuit board 150 with the base substrate), as claimed.
Park (US Patent No 11,380,651) is silent to teach a processor chip disposed on the first substrate; and a chip-to-chip wire interconnecting the processor chip and a chip stack structure that is disposed closest to the processor chip among the plurality of chip stack structures, and wherein the chip-to-chip wire electrically connects the processor chip to the chip stack structure disposed closest to the processor chip without using the wiring.
In an analogous art, Park (US Patent No 11,315,905) teaches a processor chip (interface chip 300, Figure 4, Col 4, lines 29 – 31, teaches the package substrate may be provided as a base member on which semiconductor dies and the interface chip are disposed) disposed on the first substrate; and a chip-to-chip wire (first signal extension wire 410E, Figure 5, Col 7, lines 23 – 24, teaches the first signal extension wire may be formed to connect the first signal wire to the interface chip) interconnecting the processor chip and a chip stack structure that is disposed closest to the processor chip among the plurality of chip stack structures, and wherein the chip-to-chip wire electrically connects the processor chip to the chip stack structure disposed closest to the processor chip without using the wiring (Figure 5, Col 7, lines 15-33, teaches the first signal wire may be formed to connect the first signal die pads included in the first sub-stack part to each other. The first signal wire may be formed to connect only the semiconductor dies included in the first sub-stack part to each other. The first signal wire may be electrically disconnected from the semiconductor dies included in the second sub-stack part. The first signal extension wire may be formed to connect the first signal wire to the interface chip. The first signal extension wire may be formed to extend from the first signal wire and may be bonded to the first signal chip pad of the interface chip. The first signal extension wire may be disconnected from the package substrate and may extend to be spaced apart from the package substrate. The first signal extension wire may extend to be directly connected to the interface chip without being connected to the package substrate), as claimed.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor package of Park (US Patent No 11,380,651) by incorporating the teachings of Park (US Patent No 11,315,905) by substituting the printed circuit board with the interface chip and first signal extension wire of thereby connecting the processor chip to a chip stack structure reducing the number of wirings on a substrate and the overall length of bonding wires while increasing the integrity and transmission of data signals.
Regarding claim 2, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 1, as claimed. Park (US Patent No 11,315,905) further teaches wherein a first processor chip pad, a second processor chip pad, and a third processor chip pad (chip pads 310, 320, 330; Figure 4; Col 5, lines 36-38; teaches the interface chip may include chip pads disposed on a top surface thereof) are arranged on a top surface of the processor chip, the first processor chip pad, the second processor chip pad, and the third processor chip pad are spaced apart from one another in the first direction (Col 10, lines 31-33, teaches the chip pads are arrayed in a plurality of columns, sufficient spaces between the chip pads may be provided), as claimed.
Regarding claim 3, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 2, as claimed. Park (US Patent No 11,315,905) further teaches wherein the second processor chip pad is connected to the chip stack structure through a chip-to-chip wire (Figure 4, Col 7, lines 23-27, teaches the first signal extension wire may be formed to connect the first signal wire to the interface chip. The first signal extension wire may be formed to extend from the first signal wire and may be bonded to the first signal chip pad of the interface chip), as claimed.
Regarding claim 4, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 2, as claimed. Park (US Patent No 11,315,905) further teaches wherein the second processor chip pad comprises a pad for transmitting any one of a power signal, a ground signal, and a data signal (Claim 4, Col 14, lines 38-42, teaches the semiconductor package of claim 1, wherein the first and second signal extension wires are configured to transmit data signals, and wherein the shielding wire is configured to supply one of a ground voltage and a power supply voltage), as claimed.
Regarding claim 5, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 1, as claimed. Park (US Patent No 11,380,651) further teaches wherein a number of chip stack structures provided is 2, as claimed.
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Regarding claim 6, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 1, as claimed. Park (US Patent No 11,380,651) further teaches wherein: an external connection bump (external connection terminals 180, Figure 1, Col 2 lines 66-67 – Col 3 lines 1-6, teaches the base substrate may have a first surface , for example, a top surface, on which the first to fourth chip stacks and the printed circuit board may be disposed, and a second surface , for example, a bottom surface, which faces away from the first surface and on which external connection terminals for connecting the semiconductor package with the outside may be disposed) is formed on a bottom surface of the first substrate, and a first substrate pad, a second substrate pad, and a third substrate pad (conductive pads 103-1, 103-2, 103-3; Figure 1; Col 3, lines 14-15; teaches the base substrate may include conductive pads disposed on the first surface) are formed on a top surface of the first substrate, as claimed.
Regarding claim 7, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 6, as claimed. Park (US Patent No 11,380,651) further teaches wherein: the plurality of wires comprises a first wiring that electrically connects a first processor chip pad and the external connection bump and a second wiring that electrically connects a third processor chip pad and a second chip stack structure (Figure, 1, Col 3, lines 7-10, teaches the base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks and the printed circuit board, and the external connection terminals), as claimed.
Regarding claim 8, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 7, as claimed. Park (US Patent No 11,315,905) further teaches wherein the first processor chip pad is electrically connected to the first substrate pad through a third wire (chip bonding wires 460, Figure 4, Col 10, lines 25-27, teaches the chip boding wires may be bonded to connect the third column of chip pads to the second bond fingers of the package substrate), as claimed.
Regarding claim 9, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 7, as claimed. Park (US Patent No 11,315,905) further teaches wherein the third processor chip pad is electrically connected to the second substrate pad through a fourth wire (Figure 4, Col 7, lines 41-43, teaches the third signal wire may be connected to the interface chip through the signal bond finger), as claimed.
Regarding claim 10, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 1, as claimed. Park (US Patent No 11,315,905) further teaches wherein the chip-to-chip wire is electrically connected to an uppermost semiconductor chip in a first chip stack structure from among the plurality of chip stack structures (Figure 4, Col 7 lines 17-19 + Col 7 lines 23-24, teaches the first signal wire may be formed to connect only the semiconductor dies…the first signal extension wire may be formed to connect the first signal wire to the interface chip), as claimed.
Regarding claim 11, Park (US Patent No 11,380,651) teaches A semiconductor package (Figure 1) comprising: a first substrate (base substrate 100, Figure 1, col 3, lines 7-13, teaches The base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks...and the external connection terminals. For example, the base substrate may include a printed circuit board (PCB), a redistribution layer, or the like) including a plurality of wires comprising a first wiring and a second wiring; a first chip stack structure (first chip stack 110, Figure 1, Col 2, lines 60-61) disposed on the first substrate and comprising a plurality of first semiconductor chips (first semiconductor chips 110-1 – 110-4, Figure 1, Col 3, lines 48-50 & Col 4, lines 39-40) offset-stacked in a first direction; a second chip stack structure (third chip stack 130, Figure 1, Col 2, lines 60-61) disposed on the first substrate spaced apart from the first chip stack structure in the first direction and comprising a plurality of second semiconductor chips (third semiconductor chips 130-1 – 130-4, Figure 1, Col 7, lines 19-20 & Col 7 line 66 – Col 8 line 1) offset-stacked in the first direction; an external connection bump (external connection terminals180, Figure 1, Col 2 lines 66-67 + Col 3 lines 1-6) disposed on a bottom surface of the first substrate; a first wire (first interconnectors 115, Figure 1, Col 4, lines 62-64) connecting the plurality of first semiconductor chips adjacent to each other in the first chip stack structure; a second wire (third interconnectors 135, Figure 1, Col 8, lines 18-19) connecting the plurality of second semiconductor chips adjacent to each other in the second chip stack structure, as claimed
Park (US Patent No 11,380,651) is silent to teach a processor chip disposed on the first substrate and spaced apart from the first chip stack structure; and a chip-to-chip wire connecting the processor chip and the first chip stack structure, wherein the processor chip comprises a first processor chip pad, a second processor chip pad, and a third processor chip pad, wherein the second processor chip pad is electrically connected to the chip-to-chip wire, wherein the second wiring electrically connects the processor chip to the second chip stack structure, and wherein the chip-to-chip wire electrically connects the processor chip to the first chip stack structure without using the second wiring.
In an analogous art, Park (US Patent No 11,315,905) teaches a processor chip (interface chip 300, Figure 4, Col 4, lines 29-31) disposed on the first substrate and spaced apart from the first chip stack structure; and a chip-to-chip wire (first signal extension wire 410E, Figure 4, Col 7, lines 23 – 24) connecting the processor chip and the first chip stack structure, wherein the processor chip comprises a first processor chip pad, a second processor chip pad, and a third processor chip pad (chip pads 310, 320, 330; Figure 4; Col 5, lines 36-38), wherein the second processor chip pad is electrically connected to the chip-to-chip wire (Figure 4, Col 7, lines 23-27), wherein the second wiring electrically connects the processor chip to the second chip stack structure (third signal wire 410-1 + first signal die pads 211 + first bond fingers 110 + chip pad 320 or third signal chip pad 321, Figure 4), and wherein the chip-to-chip wire electrically connects the processor chip to the first chip stack structure without using the second wiring (first signal wire 410 + die pads 210 + first signal extension wire 410E + chip pad 310 or first signal chip pad 311, Figure 4), as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor package of Park (US Patent No 11,380,651) to incorporate the teachings of Park (US Patent No 11,315,905) by substituting the printed circuit board with the interface chip and first signal extension wire of thereby connecting the processor chip to a chip stack structure reducing the number of wirings on a substrate and the overall length of bonding wires while increasing the integrity and transmission of data signals.
Regarding claim 12, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 11, as claimed. Park (US Patent No 11,315,905) further teaches wherein the second processor chip pad comprises a pad for transmitting any one of a power signal, a ground signal, and a data signal (Claim 4, Col 14, lines 38-42, teaches the semiconductor package of claim 1, wherein the first and second signal extension wires are configured to transmit data signals, and wherein the shielding wire is configured to supply one of a ground voltage and a power supply voltage), as claimed.
Regarding claim 13, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 11, as claimed. Park (US Patent No 11,380,651) further teaches further comprising a first substrate pad, a second substrate pad, and a third substrate pad (conductive pads 103-1, 103-2, 103-3; Figure 1; Col 3, lines 14-15; teaches the base substrate may include conductive pads disposed on the first surface) positioned on the first substrate, as claimed.
Regarding claim 14, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 13, as claimed. Park (US Patent No 11,315,905) further teaches wherein: the first substrate pad is electrically connected to the first processor chip pad through a third wire (chip bonding wires 460, Figure 4, Col 10, lines 25-27, teaches the chip boding wires may be bonded to connect the third column of chip pads to the second bond fingers of the package substrate), the second substrate pad is electrically connected to the third processor chip pad through a fourth wire (Figure 4, Col 7, lines 41-43, teaches the third signal wire may be connected to the interface chip through the signal bond finger), the first substrate pad is electrically connected to the external connection bump through the first wiring, and the second substrate pad is electrically connected to the second chip stack structure through the second wiring (Figure, 1, Col 3, lines 7-10, teaches the base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks and the printed circuit board , and the external connection terminals), as claimed.
Regarding claim 15, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 11, as claimed. Park (US Patent No 11,380,651) further teaches wherein each of the chip stack structures includes four semiconductor chips (Figure 1, Col 3 lines 52-53 + Col 7 lines 19-20, teaches the first chip stack includes four first semiconductor chips...the third chip stack includes four third semiconductor chips), as claimed.
Regarding claim 16, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 11, as claimed. Park (US Patent No 11,380,651) further teaches wherein each of the chip stack structures includes eight semiconductor chips (Col 3 lines 53-56 + Col 7 lines 19-23, teaches the number of semiconductor chips included in the first chip stack 110 may be variously changed to two, eight, etc…the third chip stack 130 includes four third semiconductor chips 130-1 to 130-4. However, it is to be noted that the disclosure is not limited thereto, and the number of semiconductor chips included in the third chip stack 130 may be variously changed), as claimed.
Regarding claim 17, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 11, as claimed. Park (US Patent No 11,315,905) further teaches wherein the chip-to-chip wire is electrically connected to an uppermost first semiconductor chip from among the first semiconductor chips of the chip stack structure (Figure 4; Col 7, lines 17-19 & Col 7, lines 23-24; teaches the first signal wire may be formed to connect only the semiconductor dies…the first signal extension wire may be formed to connect the first signal wire to the interface chip), as claimed.
Regarding claim 18, Park (US Patent No 11,380,651) teaches A semiconductor package (Figure 1) comprising: a first substrate (base substrate 100, Figure 1, col 3, lines 7-13, teaches The base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks...and the external connection terminals. For example, the base substrate may include a printed circuit board (PCB), a redistribution layer, or the like) including a plurality of wires comprising a first wiring and a second wiring; a first chip stack structure (first chip stack 110, Figure 1, Col 2, lines 60-61) disposed on the first substrate and comprising a plurality of first semiconductor chips (first semiconductor chips 110-1 – 110-4, Figure 1, Col 3, lines 48-50 & Col 4, lines 39-40) offset-stacked in a first direction; a second chip stack structure (third chip stack 130, Figure 1, Col 2, lines 60-61) disposed on the first substrate, spaced apart from the first chip stack structure in the first direction, and comprising a plurality of second semiconductor chips (third semiconductor chips 130-1 – 130-4, Figure 1, Col 7, lines 19-20 & Cols 7 lines 66 – Col 8 line 1) offset-stacked in the first direction; an external connection bump (external connection terminals 180, Figure 1, Col 2 lines 66-67 + Col 3 lines 1-6) disposed on a bottom surface of the first substrate; a first wire (first interconnectors 115, Figure 1, Col 4, lines 62-64) connecting the plurality of first semiconductor chips adjacent to each other in the first chip stack structure; a second wire (third interconnectors 135, Figure 1, Col 8, lines 18-19) connecting the plurality of second semiconductor chips adjacent to each other in the second chip stack structure, wherein the first substrate comprises a first substrate pad, a second substrate pad, and a third substrate pad (conductive pads 103-1, 103-2, 103-3; Figure 1; Col 3, lines 14-15) formed on a top surface thereof, wherein the second wiring electrically connects the processor chip to the second chip stack structure (Figure 1, Col 3 lines 7-20 + Col 4 lines 18-32, teaches The base substrate 100 may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks 110, 120, 130 and 140 and the printed circuit board 150, and the external connection terminals 180. For example, the base substrate 100 may include a printed circuit board (PCB), a redistribution layer, or the like...The third interconnectors 135 may electrically connect the third semiconductor chips 130-1 to 130-4 with one another and electrically connect the third chip stack 130 with the base substrate 100. In the present embodiment, the third interconnectors 135 may be bonding wires which connect the third chip pads 134 adjacent in the vertical direction with one another and connect the third chip pads 134 of the lowermost third semiconductor chip 130-1 to the third conductive pads 103-3. In other words, the third chip stack 130 may be electrically connected to the base substrate 100 by wire bonding. However, it is to be noted that the present embodiment is not limited thereto, and various types of electrical interconnectors such as leads, conductive tapes, conductive spacers and through electrodes may be used as the third interconnectors 135...The base substrate 100 may include conductive pads 103-1, 103-2, 103-3 and 103-4 disposed on the first surface 101, and conductive pads 104 disposed on the second surface 102. The conductive pads 103-1, 103-2, 103-3 and 103-4 may be for electrically connecting the first to fourth chip stacks 110, 120, 130 and 140 and the printed circuit board 150 with the base substrate), as claimed
Park (US Patent No 11,380,651) is silent to teach a processor chip disposed on the first substrate and spaced apart from the first chip stack structure; and a chip-to-chip wire connecting the processor chip and the first chip stack structure, wherein the processor chip comprises a first processor chip pad, a second processor chip pad, and a third processor chip pad, wherein the second processor chip pad is electrically connected to the chip-to-chip wire, wherein the second processor chip pad comprises a pad for transmitting any one of a power signal, a ground signal, and a data signal, and wherein the chip-to-chip wire electrically connects the processor chip to the first chip stack structure without using the second wiring.
In an analogous art, Park (US Patent No 11,315,905) teaches a processor chip (interface chip 300, Figure 4, Col 4, lines 29-31) disposed on the first substrate and spaced apart from the first chip stack structure; and a chip-to-chip wire (first signal extension wire 410E, Figure 4, Col 7, lines 23-24) connecting the processor chip and the first chip stack structure, wherein the processor chip comprises a first processor chip pad, a second processor chip pad, and a third processor chip pad (chip pads 310, 320, 330; Figure 4; Col 5, lines 36-38), wherein the second processor chip pad is electrically connected to the chip-to-chip wire (Figure 4, Col 7, lines 23-27), wherein the second processor chip pad comprises a pad for transmitting any one of a power signal, a ground signal, and a data signal (Claim 4, Col 14, lines 38-42, teaches the semiconductor package of claim 1, wherein the first and second signal extension wires are configured to transmit data signals, and wherein the shielding wire is configured to supply one of a ground voltage and a power supply voltage), and wherein the chip-to-chip wire electrically connects the processor chip to the first chip stack structure without using the second wiring (first signal wire 410 + die pads 210 + first signal extension wire 410E + chip pad 310 or first signal chip pad 311, Figure 4), as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor package of Park (US Patent No 11,380,651) to incorporate the teachings of Park (US Patent No 11,315,905) by substituting the printed circuit board with the interface chip and first signal extension wire of thereby connecting the processor chip to a chip stack structure reducing the number of wirings on a substrate and the overall length of bonding wires while increasing the integrity and transmission of data signals.
Regarding claim 19, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 18, as claimed. Park (US Patent No 11,315,905) further teaches wherein: the first substrate pad is electrically connected to the first processor chip pad through a third wire (chip bonding wires 460, Figure 4, Col 10, lines 25-27, teaches the chip boding wires may be bonded to connect the third column of chip pads to the second bond fingers of the package substrate), the second substrate pad is electrically connected to the third processor chip pad through a fourth wire (Figure 4, Col 7, lines 41-43, teaches the third signal wire may be connected to the interface chip through the signal bond finger), the first substrate pad is electrically connected to the external connection bump through the first wiring, and the second substrate pad is electrically connected to the second chip stack structure through the second wiring (Figure, 1, Col 3, lines 7-10, teaches the base substrate may include a circuit and/or wiring structure for transfer of electrical signals between the first to fourth chip stacks and the printed circuit board , and the external connection terminals), as claimed.
Regarding claim 20, Park (US Patent No 11,380,651) and Park (US Patent No 11,315,905) teach the semiconductor package of claim 18, as claimed. Park (US Patent No 11,380,651) further teaches wherein each of the chip stack structures includes four semiconductor chips (Figure 1, Col 3 lines 52-53 + Col 7 lines 19-20, teaches the first chip stack includes four first semiconductor chips...the third chip stack includes four third semiconductor chips), as claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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