DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 13, and 17 are amended. Claims 1-20 are present for examination.
Response to Arguments
Applicant’s arguments, see page 9, filed July 27, 2026, with respect to the title objection have been fully considered and are persuasive. The title objection of April 28, 2026 has been withdrawn.
Applicant’s arguments, see pages 10-12, filed July 27, 2026, with respect to the rejection(s) of claims 1, 13, and 17 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ikeda (US 2020/0388618 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define (i) the width of each word line trench of the plurality of word lines trenches (e.g. wherein the plurality of word line trenches has a first width and a second width), (ii) the isolation film has substantially slanted sidewalls within the isolation film trench of the plurality of isolation film trenches as compared to the substantially vertical sidewalls of the word line trench of the plurality of word line trenches (e.g. wherein the plurality of isolation film trenches have substantially slanted sidewalls) and (iii) wherein the isolation film trench is vertically overlapping the word line trench of the plurality of word line trenches (e.g. wherein the isolation film trench is vertically overlapping the plurality of word line trenches). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (KR 20210032843 A) in view of Ikeda (US 2020/0388618 A1).
It is noted that the Examiner is using Seong (US 2022/0238534 A1) as a convenient English translation.
Claim 1, Park discloses an integrated circuit device (semiconductor memory device 1 is an integrated circuit device, hereinafter, integrated circuit device 1, [0122], Figs. 4 and 10A) comprising:
a substrate (substrate 110, [0055], Fig. 10A) that comprises a plurality of active regions (substrate 110 further comprises a plurality of active regions 118, [0057], Fig. 10A), wherein the plurality of active regions 118 comprise a first active region (plurality of active regions 118 comprise a first active region, hereinafter, first active region 118_1, [0057], Annotated Fig. 10A) and a second active region (plurality of active regions 118 comprise a second active region, hereinafter, second active region 118_2, [0057], Annotated Fig. 10A) that is adjacent to the first active region 118_1 (second active region 118_2 is adjacent to the first active region 118_1, [0057], Annotated Fig. 10A);
a bit line (bit line structure 140 is a bit line, hereinafter, bit line 140 (i.e. further including a plurality of bit lines 147 and insulating capping lines 148), [0077], Fig. 10A) that extends on the substrate 110 (plurality of bit lines 147 of bit line 140 are on the substrate 110, [0077], Fig. 10A) in a horizontal direction (i.e. X direction) (plurality of bit lines 147 of bit line 140 are separated from each other in the X direction, [0077], Fig. 10A);
a first direct contact (direct contact conductive patterns 134 are direct contacts, wherein the direct contact conductive pattern 134 in direct contact with the first active region 118_1 is the first direct contact, hereinafter, first direct contact 134_1, [0085], Annotated Fig. 10A) connected to the first active region 118_1 (first direct contact 134_1 is connected to the first active region 118_1, [0085], Annotated Fig. 10A);
a second direct contact (first metal conductive pattern 145 is a second direct contact, hereinafter, second direct contact 145, [0077], Annotated Fig. 10A) between the first direct contact 134_1 and the bit line 140 (second direct contact 145 is between the first direct contact 134_1 and the bit line 140, [0077], Annotated Fig. 10A)
an inner nitride film (first insulating spacer 152 includes a nitride film, hereinafter, inner nitride film 152, [0087], Annotated Fig. 10A) connected to a sidewall of the first direct contact 134_1 (inner nitride film 152 is connected to a sidewall of the first direct contact 134_1, [0087], Annotated Fig. 10A) and a sidewall of the second direct contact 145 (inner nitride film 152 is connected to a sidewall of the second direct contact 145, [0087], Annotated Fig. 10A);
an isolation film (device isolation film 116 is an isolation film, hereinafter, isolation film 116, [0058], Annotated Fig. 10A) between the first active region 118_1 and the second active region 118_2 (isolation film 116 is between the first active region 118_1 and the second active region 118_2, [0058], Annotated Fig. 10A).
Park does not explicitly disclose an outer oxide film that is in contact with at least one surface of the second active region and between the inner nitride film and the second active region.
However, Ikeda discloses an outer oxide film (Ikeda, isolation walls IS3 may be formed of an oxide-nitride-oxide (ONO) multilayer, wherein the outermost wall is an outer oxide film, hereinafter, outer oxide film IS3_O2, [0019], Fig. 3K; Park, second insulating spacer 154 includes an oxide film, hereinafter, outer oxide film 154, [0087], Annotated Fig. 10A) that is in contact with at least one surface of the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is in contact with at least one surface of the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is connected to at least one surface of the second active region 118_2, [0087], Annotated Fig. 10A) and between the inner nitride film 152 and the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is between the inner nitride film IS3_N and the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is between the inner nitride film 152 and the second active region 118_2, [0087], Annotated Fig. 10A). The combination to utilize an outer oxide film between the inner nitride film and adjacent active region improves the relative positioning of the layers of the device, wherein the structure aids in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an outer oxide film between the inner nitride film and adjacent active region to aid in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
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Annotated Fig. 10A (Park) – Illustrates a first active region 118_1 that is between the second active region 118_2 and the third active region 118_3 among the plurality of active regions 118 with an isolation film 116 therebetween.
Claim 2, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses further comprising:
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and that extends in a vertical direction (i.e. Z direction) on an upper surface of the substrate 110 (contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K);
a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between a lower end portion of the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between a lower end portion of the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an inner insulating spacer (insulating film patterns 112/114 each are an inner insulating spacer, hereinafter, inner insulating spacer 112/114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film 152 (inner insulating spacer 112/114 is connected to the inner nitride film 15, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156 (a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 4, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 2.
Park/Ikeda discloses wherein:
a first portion of the gapfill insulating pattern 156 (upper portion of the gapfill insulating pattern 156 is the first portion of the gapfill insulating pattern, hereinafter, first portion of the gapfill insulating pattern 156_U, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) is between the lower end portion of the contact plug 170_2 and the second direct contact 145 (first portion of the gapfill insulating pattern 156_U is between the lower end portion of the contact plug 170_2 and the second direct contact 145, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and faces the second direct contact 145 (first portion of the gapfill insulating pattern 156_U faces the second direct contact 145, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and
a second portion of the gapfill insulating pattern 156 (bottom portion of the gapfill insulating pattern 156 is the second portion of the gapfill insulating pattern, hereinafter, second portion of the gapfill insulating pattern 156_B, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) that faces the first direct contact 134_1 has a different thickness than the first portion of the gapfill insulating pattern 156_U (second portion of the gapfill insulating pattern 156_B that faces the first direct contact 134_1 has a different thickness (i.e. thickness in the X direction) than the first portion of the gapfill insulating pattern 156_U, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 5, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses further comprising:
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and that extends in a vertical direction (i.e. Z direction) on an upper surface of the substrate 110 (contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K);
a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between a lower end portion of the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between a lower end portion of the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an inner insulating spacer (insulating film patterns 112/114 each are an inner insulating spacer, hereinafter, inner insulating spacer 112/114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film 152 (inner insulating spacer 112/114 is connected to the inner nitride film 15, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the inner nitride film 152 comprises a first portion between the first direct contact 134_1 and the gapfill insulating pattern 156 (inner nitride film 152 comprises a first portion between the first direct contact 134_1 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and a second portion connected to the lower end portion of the contact plug 170_2 (inner nitride film 152 comprises a second portion connected to the lower end portion of the contact plug 170_2, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and
the inner insulating spacer 112/114 comprises a first portion between the inner nitride film 152 and the gapfill insulating pattern 156 (inner insulating spacer 112/114 comprises a first portion between the inner nitride film 152 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and a second portion connected to the lower end portion of the contact plug 170_2 (inner insulating spacer 112/114 comprises a second portion connected to the lower end portion of the contact plug 170_2, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 6, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 5.
Park/Ikeda discloses wherein the outer oxide film 154 is connected to the lower end portion of the contact plug 170_2 (outer oxide film 154 is connected to the lower end portion of the contact plug 170_2, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 7, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses further comprising:
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and that extends in a vertical direction (i.e. Z direction) on an upper surface of the substrate 110 (contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K);
a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between a lower end portion of the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between a lower end portion of the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K);
an outer insulating spacer (insulating film patterns 112 each are an inner insulating spacer, hereinafter, outer insulating spacer 112, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) on the gapfill insulating pattern 156 and a sidewall of the contact plug 170_2 (outer insulating spacer 112 on the gapfill insulating pattern 156 and a sidewall of the contact plug 170_2, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an inner insulating spacer (insulating film patterns 114 each are an inner insulating spacer, hereinafter, inner insulating spacer 114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film 152 (inner insulating spacer 114 is connected to the inner nitride film 152, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the inner nitride film 152 and the inner insulating spacer 114 are between the outer insulating spacer 112 and the second direct contact 145 (inner nitride film 152 and the inner insulating spacer 114 are between the outer insulating spacer 112 and the second direct contact 145, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 8, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses further comprising:
an inner insulating spacer (insulating film patterns 114 each are an inner insulating spacer, hereinafter, inner insulating spacer 114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein the inner nitride film 152 is between the inner insulating spacer 114 and the bit line 140 (inner nitride film 152 is between the inner insulating spacer 114 and the bit line 140, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an outer insulating spacer (insulating film patterns 112 each are an inner insulating spacer, hereinafter, outer insulating spacer 112, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to a lower end portion of the inner nitride film 152 (outer insulating spacer 112 is connected to a lower end portion of the inner nitride film 152, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein the inner insulating spacer 114 is between the outer insulating spacer 112 and the inner nitride film 152 (inner insulating spacer 114 is between the outer insulating spacer 112 and the inner nitride film 152, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the inner nitride film 152 at least partially surrounds a lower surface of the inner insulating spacer 114 (inner nitride film 152 at least partially surrounds a lower surface of the inner insulating spacer 114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 9, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses wherein the outer oxide film 154 comprises a silicon oxide film (outer oxide film 154 comprises a silicon oxide film (i.e. oxide film may include silicon oxide), [0087] and [0127], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 10, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 1.
Park/Ikeda discloses comprising:
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and that extends in a vertical direction (i.e. Z direction) on an upper surface of the substrate 110 (contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K);
a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between a lower end portion of the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between a lower end portion of the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an outer insulating spacer (insulating film patterns 114 is an outer insulating spacer, hereinafter, outer insulating spacer 114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) on the gapfill insulating pattern 156 and a sidewall of the contact plug 170_2 (outer insulating spacer 114 is on the gapfill insulating pattern 156 and a sidewall of the contact plug 170_2, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein each of the gapfill insulating pattern 156 and the outer insulating spacer 114 comprises a silicon nitride film (gapfill insulating pattern 156 (i.e. nitride film, [0087]) and the outer insulating spacer 114 (i.e. silicon oxynitride film, [0071]) comprises a silicon nitride film, [0071] and [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 11, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 10.
Park/Ikeda discloses further comprising an inner insulating spacer (insulating film patterns 112 each are an inner insulating spacer, hereinafter, inner insulating spacer 112, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film 152 (inner insulating spacer 112 is connected to the inner nitride film 152, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the inner insulating spacer 112 comprises a silicon oxide film (inner insulating spacer 112 comprises a silicon oxide film, [0071], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 12, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 10.
Park/Ikeda discloses further comprising:
a first inner insulating spacer (insulating film patterns 112 each are a first inner insulating spacer, hereinafter, first inner insulating spacer 112, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between the gapfill insulating pattern 156 and the first direct contact 134_1 (first inner insulating spacer 112 is between the gapfill insulating pattern 156 and the first direct contact 134_1, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
a second inner insulating spacer (insulating film patterns 114 each are a second inner insulating spacer, hereinafter, second inner insulating spacer 114, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between the outer insulating spacer 112 and the second direct contact 145 (second inner insulating spacer 114 is between the outer insulating spacer 112 and the second direct contact 145, [0065], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the first inner insulating spacer 112 comprises a silicon oxide film (first inner insulating spacer 112 comprises a silicon oxide film, [0071], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and
the second inner insulating spacer 114 comprises a silicon oxide film, an air spacer, or a combination thereof (second inner insulating spacer 114 comprises a silicon oxide film (i.e. silicon oxynitride film), [0071], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 13, Park discloses an integrated circuit device (semiconductor memory device 1 is an integrated circuit device, hereinafter, integrated circuit device 1, [0122], Figs. 4 and 10A) comprising:
a substrate (substrate 110, [0055], Fig. 10A) that comprises a plurality of active regions (substrate 110 further comprises a plurality of active regions 118, [0057], Fig. 10A), wherein the plurality of active regions 118 comprise a first active region (plurality of active regions 118 comprise a first active region, hereinafter, first active region 118_1, [0057], Annotated Fig. 10A) and a second active region (plurality of active regions 118 comprise a second active region, hereinafter, second active region 118_2, [0057], Annotated Fig. 10A) that is adjacent to the first active region 118_1 (second active region 118_2 is adjacent to the first active region 118_1, [0057], Annotated Fig. 10A);
a plurality of bit lines (plurality of bit lines 147, [0077], Fig. 10A) on the substrate 110 (plurality of bit lines 147 are on the substrate 110, [0077], Fig. 10A) and separated from each other in a first horizontal direction (i.e. X direction) (plurality of bit lines 147 are separated from each other in the X direction, [0077], Fig. 10A), wherein the plurality of bit lines 147 extend in a second horizontal direction (i.e. Y direction) that intersects the first horizontal direction (i.e. X direction) (plurality of bit lines 147 extend in the Y direction that intersects the X direction, [0081], Fig. 10A);
a first direct contact (direct contact conductive patterns 134 are direct contacts, wherein the direct contact conductive pattern 134 in direct contact with the first active region 118_1 is the first direct contact, hereinafter, first direct contact 134_1, [0085], Annotated Fig. 10A) connected to the first active region 118_1 (first direct contact 134_1 is connected to the first active region 118_1, [0085], Annotated Fig. 10A);
a second direct contact (first metal conductive pattern 145 is a second direct contact, hereinafter, second direct contact 145, [0077], Annotated Fig. 10A) between the first direct contact 134_1 and a first bit line (second direct contact 145 is between the first direct contact 134_1 and the second metal conductive pattern 146 which is a first bit line, hereinafter, first bit line 146, [0077], Annotated Fig. 10A) from among the plurality of bit lines 147 (first bit line 146 is from among the plurality of bit lines 147, [0077], Annotated Fig. 10A);
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A) and that extends in a vertical direction (i.e. Z direction) on an upper surface of the substrate 110 (contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A); and
a spacer structure (insulating spacer structure 150 is a spacer structure, hereinafter, spacer structure 150, [0087], Annotated Fig. 10A) between the first bit line 146 and the contact plug 170_2 (spacer structure 150 is between the first bit line 146 and the contact plug 170_2, [0087], Annotated Fig. 10A), wherein the spacer structure 150 comprises:
an inner nitride film (first insulating spacer 152 includes a nitride film, hereinafter, inner nitride film 152, [0087], Annotated Fig. 10A) connected to a sidewall of the first direct contact 134_1 (inner nitride film 152 is connected to a sidewall of the first direct contact 134_1, [0087], Annotated Fig. 10A) and a sidewall of the second direct contact 145 (inner nitride film 152 is connected to a sidewall of the second direct contact 145, [0087], Annotated Fig. 10A); and
the outer oxide film 154 is between the inner nitride film 152 and the second active region 118_2 (outer oxide film 154 is between the inner nitride film 152 and the second active region 118_2, [0087], Annotated Fig. 10A).
Park does not explicitly disclose an outer oxide film that is in contact with at least one surface of the second active region and between the inner nitride film and the second active region.
However, Ikeda discloses an outer oxide film (Ikeda, isolation walls IS3 may be formed of an oxide-nitride-oxide (ONO) multilayer, wherein the outermost wall is an outer oxide film, hereinafter, outer oxide film IS3_O2, [0019], Fig. 3K; Park, second insulating spacer 154 includes an oxide film, hereinafter, outer oxide film 154, [0087], Annotated Fig. 10A) that is in contact with at least one surface of the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is in contact with at least one surface of the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is connected to at least one surface of the second active region 118_2, [0087], Annotated Fig. 10A) and between the inner nitride film 152 and the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is between the inner nitride film IS3_N and the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is between the inner nitride film 152 and the second active region 118_2, [0087], Annotated Fig. 10A). The combination to utilize an outer oxide film between the inner nitride film and adjacent active region improves the relative positioning of the layers of the device, wherein the structure aids in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an outer oxide film between the inner nitride film and adjacent active region to aid in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
Claim 14, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 13.
Park/Ikeda discloses wherein each of the plurality of bit lines 147 comprises a lower conductive layer (conductive semiconductor pattern 132 is a lower conductive layer, hereinafter, lower conductive layer 132, [0079], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) including a doped polysilicon film (lower conductive layer 132 includes doped polysilicon, [0079], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and an upper conductive layer (either first metal conductive pattern 145 and/or second metal conductive pattern 146 are an upper conductive layer, hereinafter, upper conductive layer 145/146) including a metal (upper conductive layer 145/146 includes a metal (i.e. titanium (Ti) and tungsten (W)), [0077], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 15, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 13.
Park/Ikeda discloses wherein the spacer structure 150 further comprises a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between a lower end portion of the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between a lower end portion of the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
the inner nitride film 152 comprises a portion between the first direct contact 134 and the gapfill insulating pattern 156 (inner nitride film 152 comprises a portion between the first direct contact 134 and the gapfill insulating pattern 156, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and
the outer oxide film 154 is on the contact plug 170_2 in the vertical direction (i.e. Z direction) (outer oxide film 154 is on the contact plug 170_2 in the Z direction, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and comprises a portion that faces the first direct contact 134 (outer oxide film 154 comprises a portion that faces the first direct contact 134, [0087], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 16, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 13.
Park/Ikeda discloses further comprising:
a third active region among the plurality of active regions (plurality of active regions 118 further comprises a third active region, hereinafter, third active region 118_3, [0057], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein the first active region 118_1 is between the second active region 118_2 and the third active region 118_3 (first active region 118_1 is between the second active region 118_2 and the third active region 118_3, [0057], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an isolation film (device isolation film 116 is an isolation film, hereinafter, isolation film 116, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between the first active region 118_1 and the second active region 118_2 (isolation film 116 is between the first active region 118_1 and the second active region 118_2, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and between the second active region 118_2 and the third active region 118_3 (isolation film 116 is between the second active region 118_2 and the third active region 118_3, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K),
wherein the isolation film 116 is between the inner nitride film 152 and the third active region 118_3 (isolation film 116 is between the inner nitride film 152 and the third active region 118_3, [0130], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 17, Park discloses an integrated circuit device (semiconductor memory device 1 is an integrated circuit device, hereinafter, integrated circuit device 1, [0122], Figs. 4 and 10A) comprising:
a substrate (substrate 110, [0055], Fig. 10A) that comprises a first active region (plurality of active regions 118 comprises a first active region, hereinafter, first active region 118_1, [0057], Annotated Fig. 10A) and a second active region (plurality of active regions 118 comprise a second active region, hereinafter, second active region 118_2, [0057], Annotated Fig. 10A);
a bit line (bit line structure 140 is a bit line, hereinafter, bit line 140 (i.e. further including a plurality of bit lines 147 and insulating capping lines 148), [0077], Fig. 10A) that extends on the substrate 110 (plurality of bit lines 147 of bit line 140 are on the substrate 110, [0077], Fig. 10A) in a horizontal direction (i.e. X direction) (plurality of bit lines 147 of bit line 140 are separated from each other in the X direction, [0077], Fig. 10A);
a first direct contact (direct contact conductive patterns 134 are direct contacts, wherein the direct contact conductive pattern 134 in direct contact with the first active region 118_1 is the first direct contact, hereinafter, first direct contact 134_1, [0085], Annotated Fig. 10A) connected to the first active region 118_1 (first direct contact 134_1 is connected to the first active region 118_1, [0085], Annotated Fig. 10A);
a second direct contact (first metal conductive pattern 145 is a second direct contact, hereinafter, second direct contact 145, [0077], Annotated Fig. 10A) between the first direct contact 134_1 and the bit line 140 (second direct contact 145 is between the first direct contact 134_1 and the bit line 140, [0077], Annotated Fig. 10A);
a contact plug (buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A) connected to the second active region 118_2 (contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A); and
a spacer structure (insulating spacer structure 150 is a spacer structure, hereinafter, spacer structure 150, [0087], Annotated Fig. 10A) between the bit line 140 and the contact plug 170_2 (spacer structure 150 is between the bit line 140 and the contact plug 170_2, [0087], Annotated Fig. 10A), wherein the spacer structure 150 comprises:
an inner nitride film (first insulating spacer 152 includes a nitride film, hereinafter, inner nitride film 152, [0087], Annotated Fig. 10A) connected to a sidewall of the first direct contact 134_1 (inner nitride film 152 is connected to a sidewall of the first direct contact 134_1, [0087], Annotated Fig. 10A) and a sidewall of the second direct contact 145 (inner nitride film 152 is connected to a sidewall of the second direct contact 145, [0087], Annotated Fig. 10A);
an inner insulating spacer (insulating film patterns 112/114 each are an inner insulating spacer, hereinafter, inner insulating spacer 112/114, [0065], Annotated Fig. 10A) connected to the inner nitride film 152 (inner insulating spacer 112/114 is connected to the inner nitride film 15, [0065], Annotated Fig. 10A); and
a gapfill insulating pattern (third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A) between the contact plug 170_2 and the first direct contact 134_1 (gapfill insulating pattern 156 is between the contact plug 170_2 and the first direct contact 134_1, [0087], Annotated Fig. 10A).
Park does not explicitly disclose an outer oxide film that is in contact with at least one surface of the second active region and between the inner nitride film and the second active region.
However, Ikeda discloses an outer oxide film (Ikeda, isolation walls IS3 may be formed of an oxide-nitride-oxide (ONO) multilayer, wherein the outermost wall is an outer oxide film, hereinafter, outer oxide film IS3_O2, [0019], Fig. 3K; Park, second insulating spacer 154 includes an oxide film, hereinafter, outer oxide film 154, [0087], Annotated Fig. 10A) that is in contact with at least one surface of the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is in contact with at least one surface of the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is connected to at least one surface of the second active region 118_2, [0087], Annotated Fig. 10A) and between the inner nitride film 152 and the second active region 118_2 (Ikeda, outer oxide film IS3_O2 is between the inner nitride film IS3_N and the second active region T1/AA, [0019], Fig. 3K; Park, outer oxide film 154 is between the inner nitride film 152 and the second active region 118_2, [0087], Annotated Fig. 10A). The combination to utilize an outer oxide film between the inner nitride film and adjacent active region improves the relative positioning of the layers of the device, wherein the structure aids in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an outer oxide film between the inner nitride film and adjacent active region to aid in avoiding charge punch through from the storage capacitor via insulating elements to the underlying bit line (Ikeda, [0031]).
Claim 18, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 17.
Park/Ikeda discloses wherein a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156 (a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claim 20, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 17.
Park/Ikeda discloses further comprising:
a third active region on the substrate 110 (on the substrate 110, the plurality of active regions 118 further comprises a third active region, hereinafter, third active region 118_3, [0057], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein the first active region 118_1 is between the second active region 118_2 and the third active region 118_3 (first active region 118_1 is between the second active region 118_2 and the third active region 118_3, [0057], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and
an isolation film (device isolation film 116 is an isolation film, hereinafter, isolation film 116, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) between the first active region 118_1 and the second active region 118_2 (isolation film 116 is between the first active region 118_1 and the second active region 118_2, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) and between the second active region 118_2 and the third active region 118_3 (isolation film 116 is between the second active region 118_2 and the third active region 118_3, [0058], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein the isolation film 116 is between the inner nitride film 152 and the third active region 118_3 (isolation film 116 is between the inner nitride film 152 and the third active region 118_3, [0130], Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Ikeda, and further in view of Kim (US 2021/0134808 A1).
Claim 3, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 2.
Park/Ikeda does not explicitly disclose wherein a second portion of the inner insulating spacer has a different thickness than the first portion of the inner insulating spacer, and wherein a second distance between the second portion of the inner insulating spacer and the substrate is greater than a first distance between the first portion of the inner insulating spacer and the substrate.
However, Kim/Ikeda/Park discloses wherein a gapfill insulating pattern (Kim, liner 215L is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 215L, [0071], Fig. 12; Park, third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and an inner insulating spacer (Kim, dielectric plug 215P is an inner insulating spacer, hereinafter, inner insulating spacer 215P, [0071], Fig. 12; Park, insulating film patterns 112/114 each are an inner insulating spacer, hereinafter, inner insulating spacer 112/114, [0065], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film (Kim, inner insulating spacer 215P is connected to the inner nitride film 216A (i.e. first spacer 216A is an inner nitride film, hereinafter, inner nitride film 216A), [0071], Fig. 12; Park, inner insulating spacer 112/114 is connected to the inner nitride film 152, [0065], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein a first portion of the inner nitride film and a first portion of the inner insulating spacer are between the first direct contact and the gapfill insulating pattern (Kim, a first portion of the inner nitride film 216A and a first portion of the inner insulating spacer 215P (i.e. inner insulating spacer 215P below lower plug 218) are between the first direct contact (i.e. lower plug 218 is a first direct contact, hereinafter, first direct contact 218) and the gapfill insulating pattern 215L, [0071], Fig. 12; Park, a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Kim/Ikeda/Park further discloses wherein a second portion of the inner insulating spacer has a different thickness than the first portion of the inner insulating spacer (Kim, second portion of the inner insulating spacer (i.e. inner insulating spacer 215P adjacent to lower plug 218) has a different thickness than the a first portion of the inner nitride film 216A, [0071], Fig. 12; Park, inner insulating spacer 112/114, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and wherein a second distance between the second portion of the inner insulating spacer and the substrate is greater than a first distance between the first portion of the inner insulating spacer and the substrate (Kim, a second distance between the second portion of the inner insulating spacer (i.e. inner insulating spacer 215P adjacent to lower plug 218) and the substrate 201 is greater than a first distance between the first portion of the inner insulating spacer 215P (i.e. inner insulating spacer 215P below lower plug 218) and the substrate 201, [0071], Fig. 12; Park, inner insulating spacer 112/114, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of thickness of an inner insulating spacer within a semiconductor interconnect device (result effective at least insofar as controlling thickness of an inner insulating spacer near adjacent bit lines enables for reduction in parasitic capacitance within a highly integrated semiconductor device, [Kim, [0004]) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed insulating spacer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 19, Park/Ikeda discloses the integrated circuit device (integrated circuit device 1, [0122], Fig. 4 and Annotated Fig. 10A, Park; Ikeda, integrated circuit device 10, [0031], Fig. 3K) of claim 18.
Park/Ikeda does not explicitly disclose wherein a second portion of the inner insulating spacer has a different thickness than the first portion of the inner insulating spacer, and wherein a second distance between the second portion of the inner insulating spacer and the substrate is greater than a first distance between the first portion of the inner insulating spacer and the substrate.
However, Kim/Ikeda/Park discloses wherein a gapfill insulating pattern (Kim, liner 215L is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 215L, [0071], Fig. 12; Park, third insulating spacer 156 is a gapfill insulating pattern, hereinafter, gapfill insulating pattern 156, [0087], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K); and an inner insulating spacer (Kim, dielectric plug 215P is an inner insulating spacer, hereinafter, inner insulating spacer 215P, [0071], Fig. 12; Park, insulating film patterns 112/114 each are an inner insulating spacer, hereinafter, inner insulating spacer 112/114, [0065], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K) connected to the inner nitride film (Kim, inner insulating spacer 215P is connected to the inner nitride film 216A (i.e. first spacer 216A is an inner nitride film, hereinafter, inner nitride film 216A), [0071], Fig. 12; Park, inner insulating spacer 112/114 is connected to the inner nitride film 152, [0065], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K), wherein a first portion of the inner nitride film and a first portion of the inner insulating spacer are between the first direct contact and the gapfill insulating pattern (Kim, a first portion of the inner nitride film 216A and a first portion of the inner insulating spacer 215P (i.e. inner insulating spacer 215P below lower plug 218) are between the first direct contact (i.e. lower plug 218 is a first direct contact, hereinafter, first direct contact 218) and the gapfill insulating pattern 215L, [0071], Fig. 12; Park, a first portion of the inner nitride film 152 and a first portion of the inner insulating spacer 112/114 are between the first direct contact 134_1 and the gapfill insulating pattern 156, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Kim/Ikeda/Park further discloses wherein a second portion of the inner insulating spacer has a different thickness than the first portion of the inner insulating spacer (Kim, second portion of the inner insulating spacer (i.e. inner insulating spacer 215P adjacent to lower plug 218) has a different thickness than the a first portion of the inner nitride film 216A, [0071], Fig. 12; Park, inner insulating spacer 112/114, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K), and wherein a second distance between the second portion of the inner insulating spacer and the substrate is greater than a first distance between the first portion of the inner insulating spacer and the substrate (Kim, a second distance between the second portion of the inner insulating spacer (i.e. inner insulating spacer 215P adjacent to lower plug 218) and the substrate 201 is greater than a first distance between the first portion of the inner insulating spacer 215P (i.e. inner insulating spacer 215P below lower plug 218) and the substrate 201, [0071], Fig. 12; Park, inner insulating spacer 112/114, [0086], Annotated Fig. 10A; Ikeda, integrated circuit device 10, [0031], Fig. 3K).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of thickness of an inner insulating spacer within a semiconductor interconnect device (result effective at least insofar as controlling thickness of an inner insulating spacer near adjacent bit lines enables for reduction in parasitic capacitance within a highly integrated semiconductor device, [Kim, [0004]) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed insulating spacer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mun (US 2022/0059543 A1) discloses further comprising:
a contact plug (Mun, bit line contact plug 212 is a contact plug, hereinafter, contact plug 212, [0085], Annotated Fig. 23; Park, buried contacts 170 are contact plugs, hereinafter, contact plugs 170, [0094], Annotated Fig. 10A) connected to the second active region (Mun, contact plug 212 is connected to the second active region 203_2, [0082], Annotated Fig. 23; Park, contact plugs 170 connected to the second active region 118_2, hereinafter, contact plug connected to the second active region 170_2, [0094], Annotated Fig. 10A) and that extends in a vertical direction on an upper surface of the substrate (Mun, contact plug 212 extends in a vertical direction on an upper surface of the substrate 201, [0085], Annotated Fig. 23; Park, contact plug connected to the second active region 170_2 extends in the Z direction on an upper surface of the substrate 110, [0097], Annotated Fig. 10A).
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Annotated Fig. 23 (Mun) – Illustrates a first active region 203_1 that is between the second active region 203_2 and the third active region 203_3 among the plurality of active regions 203 with an isolation layer 202 therebetween.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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