DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicants’ election of species III, drawn to claims 1-9 &11-19 are acknowledged. Claims 10 & 20 are drawn to an unelected species and are thus withdrawn from further examination. Claims 1-9 & 11-19 are examined herein.
Election/Restrictions
Claims 10 & 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. The conductive layer is understood to be element 190 of the instance application such that it drawn to an unelected species. Election was made without traverse in the reply filed on 06/22/2026.
Applicant’s election without traverse of species III, claims 1-9 & 11-19, in the reply filed on 06/22/2026 is acknowledged.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No 10,797,107) in view of Villa (US Patent No 11,437,097) and Frantini (US Patent Application Publication 2023/0071663A1).
Regarding claim 1, Wu (US Patent No 10,797,107) teaches a nonvolatile memory device (PCRAM, Figure 18, col 1, lines 15-18, teaches A phase change random access memory (PCRAM) is a non-volatile memory device making use of different resistive phases and heat induced phase transition between the phases of phase change materials) comprising: a substrate (substrate 10, Figure 3A, col 6, lines 21-25, teaches the substrate comprises a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate 10 is made of crystalline Si); a plurality of gate electrodes (conductive wire 140 or conductive wires 140A-140C, Figure 18, col 5, lines 19-28, teaches The conductive wires...include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof. In certain embodiments, W is used for the conductive wires) stacked on the substrate; a first conductive pillar (common electrode 110, Figure 18) that extends in a first direction perpendicular to a top surface of the substrate and intersects the plurality of gate electrodes; a second conductive pillar (common electrode 110, Figure 18) that extends in the first direction and intersects the plurality of gate electrodes, the second conductive pillar being spaced apart from the first conductive pillar; an information storage film (selector material layer 120' + PCM layers 130, Figure 18, col 3 lines 37-39 + col 3 lines 54-67+ col 4 lines 34-50, teaches a phase change memory (PCM) element includes a common electrode, a selector material layer and a plurality of PCM layers...the selector material layer includes one or more selected from the group consisting of GeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te. In other embodiments, the selector material layer is made of a material including SiO.sub.x, TiO.sub.x, AlO.sub.x, WO.sub.x, Ti.sub.xN.sub.yO.sub.z, HfO.sub.x, TaO.sub.x, NbO.sub.x, or the like, or suitable combinations thereof, where x, y and z are non-stoichiometric values. In certain embodiments, the selector material layer is a chalcogenide or a solid-electrolyte material containing one or more of Ge, Sb, S, and Te...the material of the PCM layer includes one selected from the group consisting of Ge, Ga, Sn and In, and one or more selected from the group consisting of of Sb and Te. In certain embodiments, the material of the PCM layer further includes one or more of nitrogen, bismuth and silicon oxide. For example, in some embodiments, the PCM layer is made of a binary system, such as GeSb, InSb, InSe, SbTe, GeTe, and/or GaSb; a ternary system, such as GeSbTe, InSbTe, GaSeTe, SnSbTe, InSbGe, and/or GaSbTe; or a quaternary system, such as GeSnSbTe, GeSbSeTe, TeGeSbS, GeSbTeO, and/or GeSbTeN. In certain embodiments, the PCM layer is a Ge—Sb—Te alloy (e.g., Ge.sub.2Sb.sub.2Te.sub.5) with or without doped by nitrogen and/or silicon oxide. The phase change material layer may include other phase change resistive materials, such as metal oxides including tungsten oxide, nickel oxide, copper oxide, etc) between the first conductive pillar and each of the plurality of gate electrodes and between the second conductive pillar and each of the plurality of gate electrodes, the information storage film comprising chalcogenide; a conductive layer (electrodes 160A-160C, Figure 18, col 5 lines 20-26, teaches the electrodes respectively include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof) spaced apart from the plurality of gate electrodes in the first direction, as claimed
PNG
media_image1.png
323
411
media_image1.png
Greyscale
Wu (US Patent No 10,797,107) is silent to teach a first charge dissipation layer between the first conductive pillar and the conductive layer; and a second charge dissipation layer between the second conductive pillar and the conductive layer, the second charge dissipation layer being spaced apart from the first charge dissipation layer.
In an analogous art, Villa (US Patent No 11,437,097) teaches a first charge dissipation layer (first layer 310, Figure 3, col 9 lines 45-47 + col9 line 65 - col 10 line 1, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)…The first layer may be configured to support a dissipative coupling with the second layer, such as dissipating or equalizing a voltage difference between one or more pillars and the second layer) between the first conductive pillar (pillar 220-f-1, Figure 3) and the conductive layer (second layer 320, Figure 3, col 9, lines 55-59, teaches In some examples, the second layer may be a metal layer, such as a layer of tungsten, graphene, aluminum oxide, tin, titanium nitride, or some other material or combination thereof); and a second charge dissipation layer (first layer 310, Figure 3, col 9 lines 45-47 + col9 line 65 - col 10 line 1) between the second conductive pillar (pillar 220-f-2, Figure 3) and the conductive layer, as claimed.
PNG
media_image2.png
340
502
media_image2.png
Greyscale
In another analogous art, Frantini (US Patent Application Publication 2023/0071663A1) teaches the second charge dissipation layer being spaced apart from the first charge dissipation layer (pillar selector 345, Figure 3, paragraphs 0060, teaches Each pillar may each be selectively couplable with a respective pillar row line 320 via a pillar selector 345 (e.g., a transistor or a switching component)), as claimed.
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Wu (US Patent No 10,797,107) with the teachings of Villa (US Patent No 11,437,097) and Frantini (US Patent Application Publication 2023/0071663A1) thereby having discontinuous charge dissipation layers between conductive pillars and the conductive layer.
Regarding claim 2, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the chalcogenide comprises selenium (Se), arsenic (As), and germanium (Ge) (Figure 18, col 3, lines 54-67, teaches the selector material layer includes one or more selected from the group consisting of GeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te. In other embodiments, the selector material layer is made of a material including SiO.sub.x, TiO.sub.x, AlO.sub.x, WO.sub.x, Ti.sub.xN.sub.yO.sub.z, HfO.sub.x, TaO.sub.x, NbO.sub.x, or the like, or suitable combinations thereof, where x, y and z are non-stoichiometric values. In certain embodiments, the selector material layer is a chalcogenide or a solid-electrolyte material containing one or more of Ge, Sb, S, and Te), as claimed.
Regarding claim 3, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Villa (US Patent No 11,437,097) further teaches wherein the first charge dissipation layer comprises an oxide of a material included in the first conductive pillar (col 9, lines 45-47, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)), and wherein the second charge dissipation layer comprises an oxide of a material included in the second conductive pillar (col 9, lines 45-47, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)), as claimed.
Regarding claim 4, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Villa (US Patent No 11,437,097) further teaches wherein each of the first charge dissipation layer and the second charge dissipation layer comprises an oxide-based material (col 9, lines 45-47, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)), as claimed
Regarding claim 5, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Wu (US Patent No 10,797,107) further teaches further comprising: a first conductive line (source 210, Figure 3A + 3B, col 6, lines 26-34, teaches The VFET includes a source...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain) spaced apart from the plurality of gate electrodes in the first direction, the first conductive line extending in a second direction that intersects the first direction; a second conductive line (gate 230, Figure 3A + 3B, col 6 lines 26-34 + col 6 line 54 - col 7 line 6, teaches The VFET includes a source, a channel, and a drain...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain...The gate (gate electrode layer) is includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer and the gate electrode layer. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed separately for the n-channel FET and the p-channel FET, and may use different metal layers) that extends in a third direction between the plurality of gate electrodes and the first conductive line, the third direction intersecting the first and second directions; and a selection channel pattern (channel 220, Figure 3A + 3B, col 6, lines 26-34, teaches The VFET includes a source, a channel, and a drain...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain) that extends into the second conductive line in the first direction, the selection channel pattern configured to electrically connect the first conductive line to the first conductive pillar or electrically connect the second conductive line to the first conductive pillar, as claimed.
PNG
media_image3.png
338
347
media_image3.png
Greyscale
Regarding claim 8, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the plurality of gate electrodes comprise a first wordline (conductive wire 140B, Figure 18) and a second wordline (conductive wire 140C, Figure 18) stacked on the substrate, wherein the information storage film comprises a first sub-storage film between the first wordline and the first conductive pillar, and a second sub-storage film between the second wordline and the first conductive pillar (selector material layer 120' + PCM layers 130, Figure 18), and wherein the first sub-storage film and the second sub-storage film are spaced apart from each other in the first direction (Figure 18), as claimed.
PNG
media_image4.png
373
532
media_image4.png
Greyscale
Regarding claim 9, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the plurality of gate electrodes are between the substrate and the conductive layer (Figure 3A + 18, it is understood that lower electrodeof Figure 3A is connected to lower electrode of Figure 18; and that the structure of Figure 18 is atop the structure of Figure 3A at the lower electrode), as claimed.
PNG
media_image5.png
358
447
media_image5.png
Greyscale
PNG
media_image6.png
423
222
media_image6.png
Greyscale
Regarding claim 11, Wu (US Patent No 10,797,107) teaches a nonvolatile memory device (PCRAM, Figure 18, col 1, lines 15-18, teaches A phase change random access memory (PCRAM) is a non-volatile memory device making use of different resistive phases and heat induced phase transition between the phases of phase change materials) comprising: a substrate (substrate 10, Figure 3A, col 6, lines 21-25, teaches the substrate comprises a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate 10 is made of crystalline Si); a mold stack comprising mold insulating films (first-fifth ILD layers 50B-50F, Figure 16, col 5, lines 35-48, teaches Each of the PCM layers and the conductive wires are separated by one or more interlayer dielectric (ILD) layers...A first ILD layer is disposed over the lower ILD layer, and a first conductive wire is embedded in the first ILD layer. A second ILD layer is disposed over the first ILD layer, and a second conductive wire is embedded in the second ILD layer. A third ILD layer is disposed over the second ILD layer, and a third conductive wire is embedded in the third ILD layer. A fourth ILD layer is disposed over the third ILD layer, and the fifth ILD layer is disposed over the fourth ILD layer) and gate electrodes (conductive wire 140 or conductive wires 140A-140C, Figure 16, col 5, lines 19-28, teaches The conductive wires...include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof. In certain embodiments, W is used for the conductive wires) alternately stacked on the substrate; a plurality of conductive pillars (common electrode 110, Figure 18) spaced apart from one another, each of the plurality of conductive pillars extending into the mold stack in a first direction perpendicular to a top surface of the substrate; a plurality of information storage films (selector material layer 120' + PCM layers 130, Figure 18, col 3 lines 37-39 + col 3 lines 54-67+ col 4 lines 34-50, teaches a phase change memory (PCM) element includes a common electrode, a selector material layer and a plurality of PCM layers...the selector material layer includes one or more selected from the group consisting of GeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te. In other embodiments, the selector material layer is made of a material including SiO.sub.x, TiO.sub.x, AlO.sub.x, WO.sub.x, Ti.sub.xN.sub.yO.sub.z, HfO.sub.x, TaO.sub.x, NbO.sub.x, or the like, or suitable combinations thereof, where x, y and z are non-stoichiometric values. In certain embodiments, the selector material layer is a chalcogenide or a solid-electrolyte material containing one or more of Ge, Sb, S, and Te...the material of the PCM layer includes one selected from the group consisting of Ge, Ga, Sn and In, and one or more selected from the group consisting of of Sb and Te. In certain embodiments, the material of the PCM layer further includes one or more of nitrogen, bismuth and silicon oxide. For example, in some embodiments, the PCM layer is made of a binary system, such as GeSb, InSb, InSe, SbTe, GeTe, and/or GaSb; a ternary system, such as GeSbTe, InSbTe, GaSeTe, SnSbTe, InSbGe, and/or GaSbTe; or a quaternary system, such as GeSnSbTe, GeSbSeTe, TeGeSbS, GeSbTeO, and/or GeSbTeN. In certain embodiments, the PCM layer is a Ge—Sb—Te alloy (e.g., Ge.sub.2Sb.sub.2Te.sub.5) with or without doped by nitrogen and/or silicon oxide. The phase change material layer may include other phase change resistive materials, such as metal oxides including tungsten oxide, nickel oxide, copper oxide, etc) between the mold stack and each of the plurality of conductive pillars, each of the plurality of information storage films comprising chalcogenide; a conductive layer (electrodes 160A-160C, Figure 18, col 5, lines 20-26, teaches the electrodes respectively include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof) on the mold stack; a first conductive line (source 210, Figure 3A, col 6, lines 26-34, teaches The VFET includes a source...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain) that extends on the substrate in a second direction intersecting the first direction; a second conductive line (gate 230, Figure 3A, col 6 lines 26-34 + col 6 line 54 - col 7 line 6, teaches The VFET includes a source, a channel, and a drain...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain...The gate (gate electrode layer) is includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer and the gate electrode layer. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed separately for the n-channel FET and the p-channel FET, and may use different metal layers) that extends in a third direction between the first conductive line and the mold stack, the third direction intersecting the first and second directions; a selection channel pattern (channel 220, Figure 3A, col 6, lines 26-34, teaches The VFET includes a source, a channel, and a drain...are made of the same semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In other embodiments, the channel is made of a different semiconductor material than the source and/or the drain) that extends into the second conductive line in the first direction, the selection channel pattern configured to electrically connect the first conductive line to one of the plurality of conductive pillars; and a selection gate dielectric film (gate dielectric layer 235, Figure 3A, col 6, lines 34-35 + 42-53, teaches A gate dielectric layer wraps around the channel…the gate dielectric layer includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO.sub.2—Al.sub.2O.sub.3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer includes an interfacial layer formed between the channel layers and the dielectric material) between the second conductive line and the selection channel pattern, as claimed.
PNG
media_image1.png
323
411
media_image1.png
Greyscale
Wu (US Patent No 10,797,107) is silent to teach a plurality of charge dissipation layers between the conductive layer and each of the plurality of conductive pillars, the plurality of charge dissipation layers being spaced apart from one another.
In an analogous art, Villa (US Patent No 11,437,097) teaches a plurality of charge dissipation layers (first layer 310, Figure 3, col 9 lines 45-47 + col9 line 65 - col 10 line 1, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)…The first layer may be configured to support a dissipative coupling with the second layer, such as dissipating or equalizing a voltage difference between one or more pillars and the second layer) between the conductive layer (second layer 320, Figure 3, col 9, lines 55-59, teaches In some examples, the second layer may be a metal layer, such as a layer of tungsten, graphene, aluminum oxide, tin, titanium nitride, or some other material or combination thereof) and each of the plurality of conductive pillars (pillar 220, Figure 3), as claimed.
PNG
media_image2.png
340
502
media_image2.png
Greyscale
In another analogous art, Frantini (US Patent Application Publication 2023/0071663A1) teaches the plurality of charge dissipation layers being spaced apart from one another (pillar selector 345, Figure 3, paragraphs 0060, teaches Each pillar may each be selectively couplable with a respective pillar row line 320 via a pillar selector 345 (e.g., a transistor or a switching component)), as claimed.
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Wu (US Patent No 10,797,107) with the teachings of Villa (US Patent No 11,437,097) and Frantini (US Patent Application Publication 2023/0071663A1) thereby having discontinuous charge dissipation layers between conductive pillars and the conductive layer.
Regarding claim 12, Wu (US Patent No 10,797,107), Villa (US Patent No 11,437,097), and Frantini (US Patent Application Publication 2023/0071663A1) teach the nonvolatile memory device of claim 11, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the chalcogenide comprises selenium (Se), arsenic (As), and germanium (Ge) (Figure 18, col 3, lines 54-67, teaches the selector material layer includes one or more selected from the group consisting of GeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te. In other embodiments, the selector material layer is made of a material including SiO.sub.x, TiO.sub.x, AlO.sub.x, WO.sub.x, Ti.sub.xN.sub.yO.sub.z, HfO.sub.x, TaO.sub.x, NbO.sub.x, or the like, or suitable combinations thereof, where x, y and z are non-stoichiometric values. In certain embodiments, the selector material layer is a chalcogenide or a solid-electrolyte material containing one or more of Ge, Sb, S, and Te), as claimed.
Regarding claim 13, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 11, as claimed. Villa (US Patent No 11,437,097) further teaches wherein each of the plurality of charge dissipation layers comprises an oxide of a material included in each of the plurality of conductive pillars(col 9, lines 45-47, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)), as claimed.
Regarding claim 14, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 11, as claimed. Villa (US Patent No 11,437,097) further teaches wherein each of the plurality of charge dissipation layers comprises an oxide-based material (col 9, lines 45-47, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)), as claimed.
Regarding claim 15, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 11, as claimed. Villa (US Patent No 11,437,097) further teaches wherein the conductive layer extends along a top surface of the mold stack and top surfaces of the plurality of charge dissipation layers (Figure 3), as claimed.
PNG
media_image7.png
340
500
media_image7.png
Greyscale
Regarding claim 16, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 15, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the first conductive line is between the substrate and the mold stack (Figures 3A + 18), as claimed.
PNG
media_image8.png
358
447
media_image8.png
Greyscale
PNG
media_image6.png
423
222
media_image6.png
Greyscale
Regarding claim 17, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 11, as claimed. Wu (US Patent No 10,797,107) further teaches wherein the mold insulating films protrude beyond the gate electrodes toward the conductive pillars (Figure 17, col 9 line 64 - col 10 line 5, teaches After the selector material layer is formed as shown in FIG. 13, one or more etching operations are performed to remove part of the selector material layer. Unlike the foregoing embodiments of FIG. 14, the selector material layer is divided into a plurality of selector material layers as shown in FIGS. 17 and 18. Each of the plurality of selector material layers has a ring shape, and is in contact with the PCM layer also having a ring shape), as claimed
Regarding claim 18, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 11, as claimed. Wu (US Patent No 10,797,107) further teaches further comprising: a first contact pattern (Figure 3A) that electrically connects the first conductive line to the selection channel pattern; and a second contact pattern (lower electrode 90, Figure 3A + 18, col 3, lines 30-33, teaches The common electrode is disposed on a lower electrode in some embodiments. The lower electrode is electrically connected to a drain of a field effect transistor (FET)) that electrically connects the selection channel pattern to one of the plurality of conductive pillars, as claimed.
PNG
media_image9.png
426
222
media_image9.png
Greyscale
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No 10,797,107), Villa (US Patent No 11,437,097), and Frantini (US Patent Application Publication 2023/0071663A1) in view of Fratin (US Patent Application Publication 2022/0208602A1).
Regarding claim 6, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 1, as claimed. Wu (US Patent No 10,797,107) further teaches further comprising: a first barrier layer between the information storage film and each of the plurality of gate electrodes, as claimed.
Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) are silent to teach a second barrier layer between the information storage film and the first conductive pillar.
In an analogous art, Fratin (US Patent Application Publication 2022/0208602A1) teaches a second barrier layer between the information storage film and the first conductive pillar, as claimed.
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) with the teachings of Fratin (US Patent Application Publication 2022/0208602A1) thereby having barrier layers protecting both sides of the information storage film.
Regarding claim 7, Wu (US Patent No 10,797,107) and Villa (US Patent No 11,437,097) teach the nonvolatile memory device of claim 6, as claimed. Wu (US Patent No 10,797,107) further teaches wherein each of the first barrier layer and the second barrier layer comprises a carbon layer, as claimed.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No 10,797,107) in view of Villa (US Patent No 11,437,097).
Regarding claim 19, Wu (US Patent No 10,797,107) teaches a nonvolatile memory device (PCRAM, Figure 18, col 1, lines 15-18, teaches A phase change random access memory (PCRAM) is a non-volatile memory device making use of different resistive phases and heat induced phase transition between the phases of phase change materials) comprising: a substrate (substrate 10, Figure 3A, col 6, lines 21-25, teaches the substrate comprises a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate 10 is made of crystalline Si); a mold stack comprising mold insulating films (first-fifth ILD layers 50B-50F, Figure 16, col 5, lines 35-48, teaches Each of the PCM layers and the conductive wires are separated by one or more interlayer dielectric (ILD) layers...A first ILD layer is disposed over the lower ILD layer, and a first conductive wire is embedded in the first ILD layer. A second ILD layer is disposed over the first ILD layer, and a second conductive wire is embedded in the second ILD layer. A third ILD layer is disposed over the second ILD layer, and a third conductive wire is embedded in the third ILD layer. A fourth ILD layer is disposed over the third ILD layer, and the fifth ILD layer is disposed over the fourth ILD layer) and gate electrodes (conductive wire 140 or conductive wires 140A-140C, Figure 16, col 5, lines 19-28, teaches The conductive wires...include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof. In certain embodiments, W is used for the conductive wires) alternately stacked on the substrate; a plurality of conductive pillars (common electrode 110, Figure 18) spaced apart from one another, each of the plurality of conductive pillars extending into the mold stack in a first direction perpendicular to a top surface of the substrate; a plurality of information storage films (selector material layer 120' + PCM layers 130, Figure 18, col 3 lines 37-39 + col 3 lines 54-67+ col 4 lines 34-50, teaches a phase change memory (PCM) element includes a common electrode, a selector material layer and a plurality of PCM layers...the selector material layer includes one or more selected from the group consisting of GeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te. In other embodiments, the selector material layer is made of a material including SiO.sub.x, TiO.sub.x, AlO.sub.x, WO.sub.x, Ti.sub.xN.sub.yO.sub.z, HfO.sub.x, TaO.sub.x, NbO.sub.x, or the like, or suitable combinations thereof, where x, y and z are non-stoichiometric values. In certain embodiments, the selector material layer is a chalcogenide or a solid-electrolyte material containing one or more of Ge, Sb, S, and Te...the material of the PCM layer includes one selected from the group consisting of Ge, Ga, Sn and In, and one or more selected from the group consisting of of Sb and Te. In certain embodiments, the material of the PCM layer further includes one or more of nitrogen, bismuth and silicon oxide. For example, in some embodiments, the PCM layer is made of a binary system, such as GeSb, InSb, InSe, SbTe, GeTe, and/or GaSb; a ternary system, such as GeSbTe, InSbTe, GaSeTe, SnSbTe, InSbGe, and/or GaSbTe; or a quaternary system, such as GeSnSbTe, GeSbSeTe, TeGeSbS, GeSbTeO, and/or GeSbTeN. In certain embodiments, the PCM layer is a Ge—Sb—Te alloy (e.g., Ge.sub.2Sb.sub.2Te.sub.5) with or without doped by nitrogen and/or silicon oxide. The phase change material layer may include other phase change resistive materials, such as metal oxides including tungsten oxide, nickel oxide, copper oxide, etc) between the mold stack and each of the plurality of conductive pillars, the information storage films comprising chalcogenide; and a conductive layer (electrodes 160A-160C, Figure 18, col 5, lines 20-26, teaches the electrodes respectively include one or more of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitable materials, and/or combinations thereof) on a top surface of the charge dissipation layer, wherein each of the plurality of conductive pillars protrudes beyond the top surface of the mold stack, as claimed.
PNG
media_image1.png
323
411
media_image1.png
Greyscale
Wu (US Patent No 10,797,107) is silent to teach a charge dissipation layer that extends along a top surface of the mold stack and top surfaces of the plurality of conductive pillars.
In an analogous art, Villa (US Patent No 11,437,097) teaches a charge dissipation layer (first layer 310, Figure 3, col 9 lines 45-47 + col 9 line 65 - col 10 line 1, teaches the first layer may be an example of a highly resistive layer, and may be formed by an oxide material (e.g., a thin oxide material)…The first layer may be configured to support a dissipative coupling with the second layer, such as dissipating or equalizing a voltage difference between one or more pillars) that extends along a top surface of the mold stack and top surfaces of the plurality of conductive pillars, as claimed.
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Wu (US Patent No 10,797,107) with the teachings of Villa (US Patent No 11,437,097) thereby having a charge dissipation layer atop the pillars and mold stack.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights