DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities: the recitation “there is devoid of the second insulating layer in the first trench”, should read “the second insulating layer is not present in the first trench”. Appropriate correction is required. Claim 12 is objected to because of the following informality: the recitation “the first insulating layer locates between…”, it should read “the first insulating layer is located between.... Appropriate correction is required.
Claim 16 is objected to because of the following informality: the recitation “electrically connects to…”, it should read “is electrically connected to”. Appropriate correction is required.
Claim 18 is objected to because of the following informality: the recitation “the reflective layer overlapped the first region“, it should read the reflective layer overlaps the first region”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, and 5-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (PG Pub No. US 2020/0357956 A1).
Regarding claim 1, Chen teaches an optoelectronic semiconductor device (Fig. 23), comprising:
a substrate (¶ 0079, Fig 23: 110);
a semiconductor stack (100) located on the substrate (fig. 23: 100 located on 110); a first trench and a second trench provided in the semiconductor stack (fig. 23: first trench is the far left and right second trench 6003/7001 provided in 100);
PNG
media_image1.png
414
785
media_image1.png
Greyscale
a first insulating layer (¶ 0106: 6000) filling in the first trench and covering the semiconductor stack; (¶0106 & fig. 23: 6000 fills 1st trench and covers stack 100);
a first metal layer (¶ 0084: 200) covering the first insulating layer ( fig.23, 200 covering 6000);
a second metal layer (¶ 0097: metal pad 400) covering the first insulating layer; (fig 23, 400 covering 6000); and
a second insulating layer (¶ 0083: 700) located between the first metal layer and the first insulating layer (¶ 0084, fig 23: section of 700 located in between 200 and 6000), and between the second metal layer and the first insulating layer (¶ 0084, fig 23: section of 700 between 400 and 6000)
wherein a part of the second trench is uncovered by the first insulating layer and the second insulating layer (¶0106, fig 23: portion 6003/7001 is uncovered by 6000 and 700). Regarding claim 5, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the semiconductor stack comprises a first semiconductor structure (¶ 0079: 101), a second semiconductor structure (¶ 0079: 102) and an active structure (¶ 0079: 103) between the first semiconductor structure and the second semiconductor structure (fig. 23: 103 between 101 and 102), and the second trench is provided in the semiconductor stack to reach the first semiconductor structure. (¶ 0101, fig 23: 1st 6003/7001 is provided in 100 to reach 101)
Regard claim 6, Chen teaches the optoelectronic semiconductor device of claim 5, further comprising a contact layer (¶ 0081, fig 23: 500) located on the first semiconductor structure which is exposed by the second trench ( ¶ 0035: 500 located on 101 exposed by 6003/7001). Regarding claim 7, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the first trench comprises a first depth different from a second depth of the second trench (¶ 0103 line 15, fig 23: refer to horizontal depth W).
Regarding claim 8, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the second insulating layer covers and surrounds the first insulating layer. (fig 23: 700 covers and surrounds 6000).
Regarding claim 9, The optoelectronic semiconductor device of claim 1, wherein there is devoid of the second insulating layer in the first trench (fig 23: 700 is discontinued in trench 1).
PNG
media_image2.png
305
528
media_image2.png
Greyscale
Regarding claim 11, The optoelectronic semiconductor device of claim 1, further comprising a third insulating layer (¶ 0085: 800) between the semiconductor stack and the first insulating layer ( ¶0085, fig 21: in a top-down view, at least a portion of third insulation layer 800 is in between a portion of insulation layer 6000 and a portion of semiconductor stack 100).
Regarding claim 12, The optoelectronic semiconductor device of claim 11, wherein the first insulating layer locates between the second insulating layer and the third insulating layer. ( fig 21: in top-down view, portion of 6000 between portions of 700 and 800)
PNG
media_image3.png
305
496
media_image3.png
Greyscale
Regarding claim 13, The optoelectronic semiconductor device of claim 11, wherein the third insulating layer contacts the second insulating layer ( fig 23: 800 contacts 700).
Regarding claim 14, The optoelectronic semiconductor device of claim 11, wherein the third insulating layer and the second insulating layer comprise the same material. ( ¶ 0083, 0085: 800 and 700 have at least one material in common)
Regarding claim 15, The optoelectronic semiconductor device of claim 1, further comprising a reflective layer (¶ 0091: 310; or 300/310/320 as a composite layer including reflective portion 310) is located on the semiconductor stack (fig. 23: 310 located on 100).
Regarding claim 16, The optoelectronic semiconductor device of claim 15, wherein the reflective layer electrically is connected to the first metal layer(¶ 0093 & fig. 23: 300/310/320 electrically connected to 200 through conductive element 300).
Regarding claim 17, The optoelectronic semiconductor device of claim 15, wherein the reflective layer contacts the second insulating layer. (¶ 0108, fig 23: 300/310/320 contacts 700)
Regarding claim 18, The optoelectronic semiconductor device of claim 15, wherein the semiconductor stack further comprises a current confine layer (¶ 0034, fig 23: 10/103.) having a first region and a second region surrounding the first region (implicit: any structure includes inner and outer regions), wherein the reflective layer overlaps the first region (¶ 0079,fig 23: In a top-down view, layer 103 is partially covering the first inner region of the substrate 110).
Regarding claim 19, The optoelectronic semiconductor device of claim 1, wherein the first trench comprises a first depth and the first insulating layer comprises a maximum thickness larger than or equal to the first depth (¶ 0089, Fig. 23: first trench depth and first insulating layer 6000 thickness are equal or larger than).
PNG
media_image4.png
352
395
media_image4.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim 2, is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Liu et al. (PG Pub No. 2022/0392987 A1).
Regarding claim 2, Chen teaches the optoelectronic semiconductor device of claim 1, and it teaches a first insulating layer partially corresponding to a plurality of first trenches t600 (¶ 0102, Fig 31).
Chen does not teach “wherein the first insulating layer fills up the first trench”.
Liu et al. teaches an OLED display unit including a first insulating layer 41 filling up the first trench formed between the connection electrodes (¶ 0154, Fig. 18).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor light-emitting device of Chen with first insulation layer filling up trench one of Liu, as to means to provide a more thermal stability and improving performance reliability.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Min (PG Pub No 2023/0066878 ).
Regarding claim 3, Chen teaches the optoelectronic semiconductor device of claim 1, further comprising a light-guiding structure (¶0034, active layer formed on the semiconductor stack ),
Chen does not teach “and the light-guiding layer and the semiconductor stack respectively locate on opposite sides of the substrate”.
Min teaches a LED device where the light guiding layer (400) and the semiconductor stack (150) respectively is located on the opposite side of the substrate (100)”.
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor light-emitting device of Chen with light-guiding layer configuration of Min as means to so that in case of an alternate side emission type the light is emitted through the substrate and then through the light guide portion (Min , ¶0105).
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 4, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the first metal layer comprises a first area, the second metal layer comprises a second area, and the substrate comprises a third area from a top view of the optoelectronic semiconductor device (see annotated fig. 21 below).
PNG
media_image5.png
484
387
media_image5.png
Greyscale
Chen further teaches a sum of the first area and the second area is smaller than the third area, and therefore teaches a sum of the first area and the second area to the third area is less than 1.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the ratio of 1st and 2nd areas to the 3rd area, as a means to provide structural support to the semiconductor stack.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “between 0.2 and 0.95” lies inside the range implicitly disclosed by Chen (<1).
Regarding claim 20, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the first metal layer(200) comprises a first area, the second metal layer (400) comprises a second area, and the second insulating layer (700) comprises a fourth area from a top view of the optoelectronic semiconductor device (fig 21: top view of semiconductor light-emitting device V), and a second ratio of a sum of the first area and the second area to the fourth area is between 0.5 and 1” as stated in claim 20. Chen further teaches a sum of the first area, second area is smaller than the fourth area, and therefor teaches a sum of the first area and second area to the third area is less than 1.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the ratio of 1st and 2nd areas to the 4rd area, as a means to provide structural support to the semiconductor stack.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “between 0.5 and 1” lies inside the range implicitly disclosed by Chen (<1).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Yoon (Patent No 9466765).
Regarding claim 10, Chen teaches the optoelectronic semiconductor device of claim 1, wherein the first insulating layer and second insulating layer can be comprised of organic or inorganic materials (¶ 0036).
Chen does not explicitly teach “ the first insulating layer comprises a material different from that of the second insulating layer”.
Yoon teaches an optoelectronic semiconductor device (figs. 2-3 among others)including a first insulating layer (190) comprising a material different from that of a second insulating layer(200/200a), (col. 7, line 60 to col. 8, line 13, fig. 2 190 comprises different material and formation than 200).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second insulating layer of Chen with material different from the first insulating layer, as a means to increase an area of an interface between the second insulating layer and an electrode pad (Yoon, col. 8 lines 52-60)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LYTESHIA M PRICE/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights