DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 25, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9: Since claim 6 already defined M to be a integer with M ≥1 then the expression “P(1) to P(M-1)” does not make sense and is indefinite for M=1. If Applicant intends to continue to further limit M to be M>1 as was done in the first claim element of claim 9 then this limitation should be repeated.
Regarding claim 10: Since claim 6 already defined M to be a integer with M ≥1 then the expression “P(1) to P(M-1)” does not make sense and is indefinite for M=1. If Applicant intends to continue to further limit M to be M>1 as was done in the first claim element of claim 10 then this limitation should be repeated. Claim 11 depends on claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-8, 12-15, 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Edahiro et al. (US 2008/0253181 A1).
Regarding claim 1: Edahiro (FIG. 9 and FIG. 10; [0095-0107]) teaches a method of operating a memory device comprising memory cells, the method comprising:
performing a first program pass (C-PRG in FIG. 10) on the memory cells by skipping a programming on a first subset of the memory cells (cells to be programmed to state B and cells to be programmed to state A) corresponding to a set of skipped program states, wherein a target program state of each memory cell in the first subset is one of the set of skipped program states (states A and B); and
performing a second program pass on the memory cells (B-PRG and/or A-PRG in FIG. 10).
Regarding claim 2: Edahiro teaches the method of claim 1, wherein skipping the programming on the first subset of the memory cells comprises:
applying an inhibit voltage (Vdd) to a set of bit lines corresponding to the first subset of the memory cells to inhibit the programming on the first subset of the memory cells in the first program pass ([0069, 0124, 0125]).
Regarding claim 3: Edahiro (FIG. 9) teaches the method of claim 1, wherein:
the memory cells are associated with an erased state (E) and a plurality of program states (A-C); and
the set of skipped program states comprises two or more continuous program states (A-B).
Regarding claim 4: Edahiro (FIG. 10) teaches the method of claim 3, wherein performing the first program pass on the memory cells further comprises:
programming, in the first program pass, a second subset of the memory cells (memory cells to be programmed to state C) corresponding to a remaining set of program states from the plurality of program states.
Regarding claim 6: Edahiro teaches the method of claim 3, wherein:
the plurality of program states are denoted as P(1), P(2),..., and P(2N-1), wherein N is an integer representing a number of bits stored per memory cell with N≥2 (N = 2 in FIG. 9); and
the two or more continuous program states comprise a set of program states from P(M) to P(M+K) (A=P1 and B=P2), wherein M and K are integers with M≥1 (M=1) and K≥1 (K=1).
Regarding claim 7: Edahiro teaches the method of claim 6, wherein:
the set of program states from P(M) to P(M+K) comprises an initial set of program states from P(1) to P(1+K) with M=1 (A=P1 and B=P2); and
performing the first program pass on the memory cells comprises:
programming, in the first program pass, a second subset of the memory cells (the memory cells to be programmed to state C) corresponding to a remaining set of program states from P(2+K) to P(2N-1) (C=P3, K=1 and N=2), wherein the first subset of the memory cells corresponding to the initial set of program states from P(1) to P(1+K) is inhibited from being programmed in the first program pass ([0069, 0124, 0125]).
Regarding claim 8: Edahiro teaches the method of claim 7, wherein an initial program voltage applied to a word line to program the second subset of the memory cells in the first program pass is greater than an initial program voltage applied to the word line to program the memory cells in the second program pass (FIG. 10).
Regarding claim 12: Edahiro (FIG. 9 and FIG. 10; [0095-0107]) teaches a memory device, comprising:
memory cells (memory transistors cells M0-31 in each block of a NAND flash memory in FIG. 1); and
a peripheral circuit (2 and 3 in FIG. 1, [0042-0047]) coupled to the memory cells and configured to:
perform a first program pass (C-PRG in FIG. 10) on the memory cells by skipping a programming on a first subset of the memory cells (cells to be programmed to state B and cells to be programmed to state A) corresponding to a set of skipped program states (states A and B), wherein a target program state of each memory cell in the first subset is one of the set of skipped program states; and
perform a second program pass on the memory cells (B-PRG and/or A-PRG in FIG. 10).
Regarding claim 13: Edahiro (FIG. 9 and FIG. 10) teaches the memory device of claim 12, wherein to perform the first program pass on the memory cells by skipping the programming on the first subset of the memory cells, the peripheral circuit is configured to:
apply an inhibit voltage (Vdd) to a set of bit lines corresponding to the first subset of the memory cells to inhibit the programming on the first subset of the memory cells in the first program pass ([0069, 0124, 0125]).
Regarding claim 14: Edahiro (FIG. 9 and FIG. 10) teaches the memory device of claim 12, wherein:
the memory cells are associated with an erased state (E) and a plurality of program states (A-C); and
the set of skipped program states comprises two or more continuous program states (A-B).
Regarding claim 15: Edahiro (FIG. 9 and FIG. 10) teaches the memory device of claim 14, wherein to perform the first program pass on the memory cells, the peripheral circuit is further configured to:
programming, in the first program pass, a second subset of the memory cells (memory cells to be programmed to state C) corresponding to a remaining set of program states from the plurality of program states.
Regarding claim 17: Edahiro teaches the memory device, wherein:
the plurality of program states are denoted as P(1), P(2),..., and P(2N-1), wherein N is an integer representing a number of bits stored per memory cell with N≥2 (N = 2 in FIG. 9); and
the two or more continuous program states comprise a set of program states from P(M) to P(M+K) (A=P1 and B=P2), wherein M and K are integers with M≥1 (M=1) and K≥1 (K=1).
Regarding claim 18: Edahiro teaches the memory device, wherein:
the set of program states from P(M) to P(M+K) comprises an initial set of program states from P(1) to P(1+K) with M=1 (A=P1 and B=P2); and
to perform the first program pass on the memory cells, the peripheral circuit is further configured to:
to program, in the first program pass, a second subset of the memory cells (the memory cells to be programmed to state C) corresponding to a remaining set of program states from P(2+K) to P(2N-1) (C=P3, K=1 and N=2), wherein the first subset of the memory cells corresponding to the initial set of program states from P(1) to P(1+K) is inhibited from being programmed in the first program pass ([0069, 0124, 0125]).
Regarding claim 19: Edahiro teaches the memory device, wherein an initial program voltage applied to a word line to program the second subset of the memory cells in the first program pass is greater than an initial program voltage applied to the word line to program the memory cells in the second program pass (FIG. 10).
Regarding claim 20: Edahiro (method of FIG. 9 and FIG. 10; [0095-0107] using the device of FIG. 1, [0042-0047] and FIG. 17, [0165-0168]) teaches a system, comprising:
a memory device (a memory core or array of FIG. 1 in the flash memory of FIG. 17) configured to store data and comprising:
memory cells (memory transistors M0:31 in each string of a NAND memory block BLK as illustrated in FIG. 1); and
a peripheral circuit (2 and 3 illustrated in FIG. 1 or FIG. 17) coupled to the memory cells and configured to:
perform a first program pass (C-PRG in FIG. 10) on the memory cells by skipping a programming on a first subset of the memory cells (cells to be programmed to state B and cells to be programmed to state A) corresponding to a set of skipped program states, wherein a target program state of each memory cell in the first subset is one of the set of skipped program states (states A and B); and
perform a second program pass on the memory cells (B-PRG and/or A-PRG in FIG. 10);
a memory controller (5 in FIG. 17) coupled to the memory device and configured to control an operation of the memory device.
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of programming the first subset of the memory cells and the second subset of the memory cells in the second program pass in combination with the other limitations thereof as is recited in the claim.
Regarding claim 16: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the peripheral circuit is further configured to program the first subset of the memory cells and the second subset of the memory cells in the second program pass in combination with the other limitations thereof as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827