DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims Status
Claims 1-2, 4, 6, 8-12, 14-18 and 20-25 are currently pending and being examined.
Claim Objections
The objection of Claims 16-20 of the last Office action is withdrawn. Claim 16 has been amended to overcome the objection.
Claim Rejections - 35 USC § 112
The rejection of Claim 9 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph is withdrawn. Claim 9 has been amended to overcome the rejection.
Allowable Subject Matter
Claims 10 and 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Re claim 10, the prior art cannot anticipate, or render obvious the limitations of: wherein each of the first dummy bonding structures comprises a respective metallic dummy pad portion and a respective metallic dummy via portion that vertically protrudes downward from the respective metallic dummy pad portion and has a lesser vertical extent than the respective metallic via portion of the one of the first integrated metal bonding pads, in combination with the additionally claimed features of claims 1 and 10.
A. In Re claims 21-24, they are objected to due to their dependence from claim 10.
Claim 25 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: Re claim 25, the prior art cannot anticipate, or render obvious the limitations of: forming an array of first dummy bonding pads within dummy cavities comprising the pad cavities and the dummy via cavities formed underneath the second openings, wherein each of the first dummy bonding structures comprises a respective metallic dummy pad portion located in the respective pad cavity and a respective metallic dummy via portion located in the respective dummy via cavity, in combination with the additionally claimed features of claim 25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 12; and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo (US 2006/0094245 A1-of record).
Re claim 1, Seo discloses in FIG. 1E a semiconductor structure (semiconductor device; [0020]) comprising a first semiconductor die (portion of semiconductor device shown), wherein the first semiconductor die comprises:
first semiconductor devices (MOS transistors 10; [0011]) located over a first substrate (semiconductor substrate; [0011]);
first metal interconnect structures (lower metal lines 12; [0003] and [0011]) embedded in first dielectric material layers (unlabeled layers below 14) that overlie the first semiconductor devices (10);
a first bonding-level dielectric layer (layer laminate 14/16a/16b; [0011]-[0013]) that overlies the first dielectric material layers (unlabeled layers below 14); and
an array of first integrated metal bonding pads (unseen Al, Cu metal lines formed in 26; [0019] and [0021]) embedded within the first bonding-level dielectric layer (layer laminate 14/16a/16b) and electrically connected to a respective (each) one of the first metal interconnect structures (lower metal lines 12),
wherein each of the first integrated metal bonding pads (unseen Al, Cu metal lines formed in 26) comprises:
a respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24; [0019] and [0021]) that extends through a lower portion (bottom) of the first bonding-level dielectric layer (layer laminate 14/16a/16b); and
a respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22; [0019] and [0021]) having a convex sidewall (bowl shape; [0018]) that extends through an upper portion (top) of the first bonding-level dielectric layer (layer laminate 14/16a/16b).
For the record, the unlabeled layers below layer (12) and embedding first metal interconnect structures (lower metal lines 12) are being identified as being first dielectric material layers, otherwise, the first semiconductor devices (MOS transistors 10) would be short-circuited to each other.
Re claim 2, Seo discloses the semiconductor structure of Claim 1, wherein the convex sidewall (bowl shape) of the respective metallic pad portion (portion of unseen metal lines formed in trench 22) has a uniform radius of curvature throughout (symmetric with respect to a center line perpendicular to the first substrate); and centers (mid-points) of curvature of the convex sidewall (bowl shape) of the respective metallic pad portion (portion of unseen metal lines formed in trench 22) are located entirely within a horizontal plane (of 16b) including a top surface (upper plane) of the first bonding-level dielectric layer (layer laminate 14/16a/16b).
Re claim 12, Seo discloses the semiconductor structure of Claim 1, wherein the first integrated metal bonding pads (unseen metal lines formed in 26) have planar top surfaces (planarized; [0021]) within a horizontal plane (upper surface) including a top surface (upper surface of 16b) of the first bonding-level dielectric layer (layer laminate 14/16a/16b).
Re claim 16, Seo discloses in FIGS. 1-A1E a method of forming a semiconductor structure (semiconductor device; [0020]), comprising:
forming (FIG. 1A) first semiconductor devices (MOS transistors 10; [0011]) located over a first substrate (semiconductor substrate; [0011]);
forming (FIG. 1A) first dielectric material layers (unlabeled layers below 14) embedding first metal interconnect structures (lower metal lines 12; [0003] and [0011]) over the first semiconductor devices (MOS transistors 10), wherein the first metal interconnect structures (lower metal lines 12) are electrically connected to the first semiconductor devices (MOS transistors 10);
forming (FIG. 1A) a first bonding-level dielectric layer (layer laminate 14/16a/16b; [0011]-[0013]) over the first dielectric material layers (unlabeled layers below 14);
forming (FIG. 1A) an etch mask layer (20; [0011]) comprising an array of discrete openings (W; [0016]) therethrough over the first bonding-level dielectric material layers (layer laminate 14/16a/16b);
forming (FIG. 1C) pad cavities (trenches 22; [0018]) in an upper portion (16b) of the first bonding-level dielectric layer (layer laminate 14/16a/16b) underneath (below) the openings (W) in the etch mask layer (20) by performing an isotropic etch process (wet etching; [0018]);
forming (FIG. 1D) via cavities (24; [0019]) in a lower portion (16a) of the first bonding-level dielectric layer (layer laminate 14/16a/16b) by performing an anisotropic etch process (dry etching; [0019]) through the pad cavities (trenches 22) while the etch mask layer (20) is present;
removing (FIG. 1E) the etch mask layer (20; [0020]); and
forming (FIG. 1E) an array of first integrated metal bonding pads (unseen Al, Cu metal lines formed in 26; [0019] and [0021]) within a combination (both) of the pad cavities (trenches 22) and the via cavities (24).
For the record, the unlabeled layers below layer (12) and embedding first metal interconnect structures (lower metal lines 12) are being identified as being first dielectric material layers, otherwise, the first semiconductor devices (MOS transistors 10) would be short-circuited to each other.
Re claim 17, Seo discloses the method of Claim 16, wherein each of the first integrated metal bonding pads (unseen Al, Cu metal lines formed in 26) comprises: a respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24; [0019] and [0021]) that is formed within a respective one (each) of the via cavities (24); and a respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22; [0019] and [0021]) that is formed within a respective (each) one of the pad cavities (trenches 22).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 6, 8, 11, 14-15; 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of ISHIKAWA et al (US 2022/0336394 A1-of record, hereafter Ishikawa) and Park (US 2005/0073053 A1-of recod).
Re claim 4, Seo discloses the semiconductor structure of Claim 1, wherein the convex sidewall (bowl shape) has a bottom periphery (lower surface) that coincides (interfaces) with a top periphery (upper surface) of the respective metallic via portion (portion of unseen metal lines formed in 24), wherein: the first bonding-level dielectric layer (layer laminate 14/16a/16b) comprises a layer stack that includes a first silicate glass layer (16a; [0014]) and a low-k layer (16b; [0015]) that overlies the first silicate glass layer (16a).
Seo fails to disclose the first bonding-level dielectric layer (layer laminate 14/16a/16b) comprises a first silicon carbide nitride layer that overlies the first silicate glass layer (16a); and a boundary between the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) and the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) is located entirely within the first silicon carbide nitride layer.
However,
A. Ishikawa discloses in FIG. 3H a semiconductor structure comprising low-k interconnect dielectric material layers (dielectric material having a dielectric constant less than 5, e.g. SiCN; [0167] and [0251]).
And,
B. Park discloses in FIG. 1F a semiconductor structure comprising first integrated metal bonding pads (33c; [0016]-[0017]) comprising a boundary (interface) between the respective metallic via portion (lower portion of 33c formed in 24/25a/28; [0013] and [0016]) and the respective metallic pad portion (upper portion of 33c formed in 28; [0016]) is located entirely within an upper layer (28; [0013] and [0016]) of a first bonding-level dielectric layer (layer laminate 24/25a/28; [0013] and [0016]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Seo by, firstly, using the SiCN material of Ishikawa as the material of the low-k layer of Seo, such that the first bonding-level dielectric layer (layer laminate 14/16a/16b) comprises a first silicon carbide nitride layer, a dielectric material having a dielectric constant less than 5, that overlies the first silicate glass layer (16a); and a boundary between the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24), to reduce RC delay of the first integrated metal bonding pads (Ishikawa; [0167]), and to act as diffusion blocker of the first integrated metal bonding pads (Ishikawa; [0251]); and secondly, by using the first integrated metal bonding pad formation of Park for the first integrated metal bonding pads of Seo, such that a boundary between the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) and the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) is located entirely within the first silicon carbide nitride layer (of Ishikawa), to form capacitor structures that have improved leakage current properties for storage of information in semiconductor structures comprising IC circuits (Park; [0003] and [0035]).
Re claim 6, Seo discloses the semiconductor structure of Claim 1.
But, fails to disclose wherein the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) comprises an annular planar bottom surface having an inner periphery that coincides with a top periphery of the respective metallic via portion; and wherein an outer periphery of the annular planar bottom surface coincides with a bottom periphery of the convex sidewall.
However, Park would render these limitations obvious since the respective metallic pad portion (33c) comprises an annular planar bottom surface (flat portion of 33c on 25a) having an inner periphery (left/right inner ends) that coincides (interface) with a top periphery (inner upper left/right ends) of the respective metallic via portion (portion of 33c formed in 28), as would be part of the capacitor structures discussed for claim 4.
Re claim 8, Seo and Ishikawa disclose the semiconductor structure of Claim 6, wherein: the first bonding-level dielectric layer (layer laminate 14/16a/16b) comprises a layer stack that includes a first silicate glass layer (Seo: 16a) and a first silicon carbide nitride layer (Ishikawa: SiCN as 16b of Seo) that overlies the first silicate glass layer (16a); and a boundary (interface) between the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) and the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) is located within a horizontal plane (entire thickness of layer laminate 14/16a/16b) including an interface between the first silicate glass layer (16a) and the first silicon carbide nitride layer (SiCN 16b), as would be part of the reduced RC delay/diffusion blocking structures discussed for claim 5.
Re claim 11, Seo discloses the semiconductor structure of Claim 1.
But, fails to disclose wherein a ratio of a height of the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) to a height of the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) is in a range from 1/4 to 4.
However, Ishikawa discloses a height (thickness; [0174]) of the respective metallic pad portion (958B; [0197]) of 300-3000 nm ([0174]) and a height (thickness) of the respective metallic via portion (968; [0173) of 105-3050 nm ([0168]-[0169]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Seo by the using the heights of the respective metallic pad portion (958B; [0197]) of 300-3000 nm ([0174]) and of the respective metallic via portion as disclosed by Ishikawa, such that a ratio of a height of the respective metallic pad portion (portion of unseen Al, Cu metal lines formed in trench 22) to a height of the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) is in a range from 1/4 to 4, to effectively change the overall thickness of the semiconductor structure.
Re claims 14-15, Seo discloses the semiconductor structure of Claim 1.
But, fails to disclose the semiconductor structure further comprising a second semiconductor die that is bonded to the first semiconductor die, wherein the second semiconductor die comprises: second semiconductor devices located over a second substrate; second metal interconnect structures embedded in second dielectric material layers and electrically connected to the second semiconductor devices; a second bonding-level dielectric layer located over the second dielectric material layers; and an array of second metal bonding pads embedded within the second bonding-level dielectric layer and electrically connected to a respective one of the second metal interconnect structures and bonded to a respective one of the first integrated metal bonding pads by metal-to-metal bonding; and wherein each of the second metal bonding pads comprises: a respective metallic via portion that extends through a distal portion of the second bonding-level dielectric layer; and a respective metallic pad portion having a convex sidewall that extends through a proximal portion of the second bonding-level dielectric layer.
However, Ishikawa discloses in FIG. 44 a bonded semiconductor structure comprising a first semiconductor die (700; [0473) and a second semiconductor die (900; [0473).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Seo, again using Ishikawa, by applying its bonding teachings to bond a second identical semiconductor structure of Seo to itself for stacked semiconductor structures, or to bond the second semiconductor die of Ishikawa to the first semiconductor die of Seo, such that the semiconductor structure further comprises a second semiconductor die that is bonded to the first semiconductor die, wherein the second semiconductor die comprises: second semiconductor devices located over a second substrate; second metal interconnect structures embedded in second dielectric material layers and electrically connected to the second semiconductor devices; a second bonding-level dielectric layer located over the second dielectric material layers; and an array of second metal bonding pads embedded within the second bonding-level dielectric layer and electrically connected to a respective one of the second metal interconnect structures and bonded to a respective one of the first integrated metal bonding pads by metal-to-metal bonding; and wherein each of the second metal bonding pads comprises: a respective metallic via portion that extends through a distal portion of the second bonding-level dielectric layer; and a respective metallic pad portion having a convex sidewall that extends through a proximal portion of the second bonding-level dielectric layer, creating a memory die and a logic die semiconductor structure (Ishikawa; [0473]).
Re claim 18, Seo and Ishikawa disclose the method of Claim 16, wherein the first bonding-level dielectric layer comprises a layer stack that includes a first silicate glass layer and a first silicon carbide nitride layer that overlies the first silicate glass layer (see claim 4).
But, fails to disclose wherein the isotropic etch process (wet etching) etches the
first silicon carbide nitride layer selective to the first silicate glass layer (16a).
However, since Seo, Ishikawa and Park all disclose an isotropic etch process (wet etching) to form convex sidewalls without etching immediately adjacent low-k material layers, it would have been obvious that the method of Seo, Ishikawa and Park would result in the isotropic etch process (wet etching) etching the first silicon carbide nitride layer selective to the first silicate glass layer (16a) for the formation of the structures discussed for claim 4.
Re claim 20, Seo and Ishikawa disclose the method of Claim 16, further comprising: providing a second semiconductor die which comprises: second semiconductor devices located over a second substrate, second metal interconnect structures embedded in second dielectric material layers and electrically connected to the second semiconductor devices, a second bonding-level dielectric layer located on the second dielectric material layers, and an array of second metal bonding pads embedded within the second bonding-level dielectric layer and electrically connected to a respective one of the second metal interconnect structures; and bonding the second metal bonding pads to the first integrated metal bonding pads by metal-to-metal bonding (see claims 14-15).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Chen et al (US 2021/0035907 A1-of record, hereafter Chen).
Re claim 9, Seo discloses the semiconductor structure of Claim 1.
But, fails to disclose wherein: the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) has a straight sidewall that extends straight from a top periphery (upper outer surface) of the respective metallic via portion to a bottom periphery (lower outer surface) of the respective metallic via portion; and the straight sidewall has a uniform taper angle with respective to a vertical direction in a range from 0.1 degree to 5 degrees.
However,
Chen discloses in FIG. 2F (with references to FIG. 1C) a semiconductor structure comprising wherein: a respective metallic via portion (486; [0046]) has a straight sidewall (left/right planes of 480 as in 280; [0031]; [0046] and [0048]) that extends straight from a top periphery (upper outer surface) of the respective metallic via portion to a bottom periphery (lower outer surface) of the respective metallic via portion (486); and the straight sidewall (left/right planes of 480 as in 280) has a uniform taper angle with respective to a vertical direction in a range from 0.1 degree to 5 degrees (1-6 degrees; [0031]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Seo by using the uniform taper angle with respective to a vertical direction in a range from 0.1 degree to 5 degrees of Chen, such that the respective metallic via portion (portion of unseen Al, Cu metal lines formed in 24) has a straight sidewall that extends straight from a top periphery (upper outer surface) of the respective metallic via portion to a bottom periphery (lower outer surface) of the respective metallic via portion, increasing the area of the top periphery (upper outer surface) of the respective metallic via portion, which reduces if resistance and improves RC delay.
Response to Arguments
Applicant's arguments filed 7/27/2026 have been fully considered but they are not persuasive for the following reason(s):
Essentially, for each of claims 1; and 16, the applicant argues that the metal lines (unseen Al, Cu metal lines formed in 26) of Seo are not “bonding pads”. The arguments reference the fact that the Seo metal line bonding pads of Seo are not explicitly disclosed to be used for bonding two objects to each other.
However, the examiner, respectfully, disagrees with these arguments sing the materials of the metal lines of Seo are copper, as are the disclosed by the bonding pads disclosed by the instant specification. The applicant’s interpretation of a “bonding pad” precludes other uses of “bonding pads”, such “bonding pads” for wiring bonding.
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987). See MPEP § 2114 [R-1].
Therefore, the examiner concludes that’s that the metal lines (unseen Al, Cu metal lines formed in 26) of Seo are indeed “bonding pads”. And thus, the rejections of claims 1; and 16 are maintained. Likewise, the rejections of claims 2, 4, 6, 8-9, 11-12, 14; 18 and 20, depending from claims 1; and 16, respectively, are also maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408)918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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