DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on 05/27/2026 is acknowledged.
Claims 8-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/27/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0132281 to Kato.
With respect to claim 1, Kato discloses a semiconductor device (see the annotated Fig. 7 below) (Kato, Figs. 4-7, ¶0020-¶0038, ¶0039-¶0097), comprising:
a semiconductor substrate (41) (Kato, Figs. 6-7, ¶0044-¶0048, ¶0055);
a front surface electrode (422) (Kato, Fig. 6-7, ¶0052, ¶0055-¶0057) containing Al and provided to a front surface (41a) of the semiconductor substrate (41);
a first metal layer (423, NiP) (Kato, Fig. 7, ¶0055, ¶0058-¶0060) containing Ni and provided on the front surface electrode (422); and
a second metal layer (424, Ni3P, the P-rich Ni layer) (Kato, Fig. 7, ¶0078-¶0079) containing Ni and provided on the first metal layer (423), wherein
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a surface roughness (e.g., uneven portion 4231) (Kato, Fig. 7, ¶0079) of the first metal layer (423) is larger than a surface roughness (e.g., uneven portion of the P-rich Ni layer 424) of the second metal layer (424).
Regarding claim 6, Kato discloses a power conversion device (Kato, Figs. 1-5, ¶0020-¶0041), comprising:
a main conversion circuit (e.g., the inverter 6) (Kato, Figs. 1-5, ¶0033-¶0035, ¶0039-¶0042) including the semiconductor device (e.g., IGBT 11 and diode 12) according to claim 1, converting (e.g., DC-AC conversion circuit) (Kato, Fig. 1, ¶0033) electrical power inputted from a power source (2), and outputting the electrical power to a load;
a drive circuit (Kato, Fig. 1, ¶0037) outputting a drive signal for driving the semiconductor device (e.g., corresponding IGBT 11/diode 12) to the semiconductor device; and
a control circuit (Kato, Fig. 1, ¶0038) outputting a control signal for controlling the drive circuit to the drive circuit.
With respect to claim 7, Kato discloses a method of manufacturing a semiconductor device (e.g., IGBT, see the annotated Fig. 7 above) (Kato, Figs. 4-7, ¶0022-¶0025, ¶0039-¶0097, ¶0107-¶0114), comprising:
a step of forming a front surface electrode (422) (Kato, Fig. 6-7, ¶0052, ¶0055-¶0057) containing Al on a front surface (41a) of a semiconductor substrate (41) (Kato, Figs. 6-7, ¶0045-¶0048, ¶0055);
a step of forming a first metal layer (423, NiP) (Kato, Fig. 7, ¶0055, ¶0058-¶0060) containing Ni on the front surface electrode (422); and
a step of forming a second metal layer (424, Ni3P, the P-rich Ni layer) (Kato, Fig. 7, ¶0078-¶0079) containing Ni on the first metal layer (423),
wherein
a surface roughness (e.g., uneven portion 4231) (Kato, Fig. 7, ¶0079) of the first metal layer (423) is larger than a surface roughness (e.g., uneven portion of the P-rich Ni layer 424) of the second metal layer (424).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2025/0132281 to Kato in view of Urano et al. (US 20100240213, hereinafter Urano).
Regarding claim 2, Kato discloses the semiconductor device according to claim 1. Further, Kato discloses the semiconductor device, further comprising a front surface-side noble metal (e.g., gold (Au) electrode material diffused into solder) (Kato, Fig. 7, ¶0059) containing nobler metal (Au) than the second metal layer (Ni), but does not specifically disclose a front surface-side noble metal film provided on the second metal layer.
However, Urano teaches forming a power semiconductor device (Urano, Fig. 1, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0081, ¶0089, ¶0098) comprising an emitter electrode (6) including a nickel-plated film (11) and a gold-plated film (12) provided on the nickel- plated film (11), to prevent oxidation on the plated nickel film (11), and to improve adhesion with solder.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kato by forming an emitter electrode including a gold-plated film provided on the nickel-plated film as taught by Urano to have the semiconductor device, wherein a front surface-side noble metal film provided on the second metal layer, in order to prevent oxidation on the plated nickel film and to improve adhesion with solder (Urano, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0067, ¶0081, ¶0089, ¶0098).
Regarding claim 3, Kato discloses the semiconductor device according to claim 1. Further, Kato discloses the semiconductor device, further comprising: a back surface electrode (e.g., collector electrode 43) (Kato, Figs. 4, 7, ¶0048-¶0049) provided to a back surface (41b) of the semiconductor substrate (41), but does not specifically disclose a back surface electrode containing Al and; a third metal layer containing Ni and provided on the back surface electrode; and a fourth metal layer containing Ni and provided on the third metal layer, wherein a surface roughness of the third metal layer is larger than a surface roughness of the fourth metal layer.
However, Urano teaches forming a power semiconductor device (Urano, Fig. 1, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0081, ¶0089, ¶0098) comprising an emitter electrode (6) including a nickel-plated film (11) and a gold-plated film (12) provided on the nickel- plated film (11), and a collector electrode (91/92) (Urano, Fig. 1, ¶0067, ¶0070-¶0073, ¶0077, ¶0080-¶0081) on a back surface of the semiconductor substrate (1) and including the back surface electrode (91) containing Al, and a third metal layer (92) containing Ni and provided on the back surface electrode (91); and a fourth metal layer (11) containing Ni and provided on the third metal layer (91), and a gold-plated film (12), to prevent oxidation on the plated nickel film, and to improve adhesion with solder.
Further, Kato teaches forming copper wiring (50/60) (Kato, Figs. 4, 7, ¶0062) that are soldered to the front surface electrode (e.g., emitter electrode 41) and back surface electrode (e.g., collector electrode 43), to provide a heat dissipation function. The uneven portions of the first/second metal layers (423/424) (Kato, Fig. 7, ¶0080-¶0081) of the front surface electrode (41) control grain size of the solder (91) between the wiring (50) made of copper and the front surface electrode (41), to hinder copper diffusion, to improve electromigration lifetime, and to improve performance of the IGBT/diode device.
Thus, Kato recognizes that uneven portions of the metal layers between the front/back surface electrode and solders impact grain sizes of the solders between the front/back surface electrode and copper wirings, and performance of the IGBT/diode device. Thus, uneven portions of the metal layers between the front/back surface electrode and solders are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the uneven portions of the metal layers between the front/back surface electrode and solders as Kato has identified the uneven portions of the metal layers between the front/back surface electrode and solders as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at uneven portions of the metal layers between the front/back surface electrode and solders, such that a surface roughness of the third metal layer is larger than a surface roughness of the fourth metal layer, in order to hinder copper diffusion, to improve electromigration lifetime, and to improve performance of the IGBT/diode device as taught by Kato (¶0080-¶0081, ¶0093-¶0096) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kato by forming a collector electrode including Al back surface electrode, a third metal layer including nickel, and a fourth metal layer including nickel as taught by Urano, and controlling the uneven portions of the third and fourth metal layers between the back surface electrode and solders as taught y Kato to have the semiconductor device, further comprising: a back surface electrode containing Al and; a third metal layer containing Ni and provided on the back surface electrode; and a fourth metal layer containing Ni and provided on the third metal layer, wherein a surface roughness of the third metal layer is larger than a surface roughness of the fourth metal layer, in order to provide a power semiconductor device with improved performance characteristics; and to control grain size of solders to hinder copper diffusion, to improve electromigration lifetime, and to improve performance of the IGBT/diode device (Urano, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0067, ¶0081, ¶0089, ¶0098; Kato, ¶0080-¶0081, ¶0093-¶0096).
Regarding claim 4 and 5, Kato in view of Urano discloses the semiconductor device according to claim 3. Further, Kato does not specifically disclose the semiconductor device, further comprising a back surface-side noble metal film containing nobler metal than the fourth metal layer and provided on the fourth metal layer (as claimed in claim 4); wherein a composition of the third metal layer is a same as a composition of the first metal layer, and a composition of the fourth metal layer is a same as a composition of the second metal layer (as claimed in claim 5).
However, Urano teaches forming a power semiconductor device (Urano, Fig. 1, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0081, ¶0089, ¶0098) comprising an emitter electrode (6) including a nickel-plated film (11) and a gold-plated film (12) provided on the nickel- plated film (11), and a collector electrode (91/92) (Urano, Fig. 1, ¶0067, ¶0070-¶0073, ¶0077, ¶0080-¶0081) on a back surface of the semiconductor substrate (1) and including the back surface electrode (91) containing Al, and a third metal layer (92) containing Ni and provided on the back surface electrode (91); and a fourth metal layer (11) containing Ni and provided on the third metal layer (91), and a gold-plated film (12), to prevent oxidation on the plated nickel film, and to improve adhesion with solder.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kato/Urano by forming the collector electrode and the emitter electrode including Al front/back electrode layer, first/third metal layer including nickel, second/fourth metal layer including nickel, and a gold-plated film provided on the second/fourth metal layer as taught by Urano to have the semiconductor device, further comprising a back surface-side noble metal film containing nobler metal than the fourth metal layer and provided on the fourth metal layer (as claimed in claim 4); wherein a composition of the third metal layer is a same as a composition of the first metal layer, and a composition of the fourth metal layer is a same as a composition of the second metal layer (as claimed in claim 5), in order to provide a power semiconductor device with improved performance characteristics comprising front/back surface electrode with improved adhesion to solder (Urano, ¶0003, ¶0012, ¶0030-¶0031, ¶0048-¶0049, ¶0066-¶0067, ¶0081, ¶0089, ¶0098).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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